Monolithic 3D Integration of Analog RRAM-Based Computing-in-Memory and Sensor for Energy-Efficient Near-Sensor Computing.

In the era of the Internet of Things, vast amounts of data generated at sensory nodes impose critical challenges on the data-transfer bandwidth and energy efficiency of computing hardware. A near-sensor computing (NSC) architecture places the processing units closer to the sensors such that the generated data can be processed almost in situ with high efficiency. This study demonstrates the monolithic three-dimensional (M3D) integration of a photosensor array, analog computing-in-memory (CIM), and Si complementary metal-oxide-semiconductor (CMOS) logic circuits, named M3D-SAIL. This approach exploits the high-bandwidth on-chip data transfer and massively parallel CIM cores to realize an energy-efficient NSC architecture. The 1st layer of the Si CMOS circuits serves as the control logic and peripheral circuits. The 2nd layer comprises a 1 k-bit one-transistor-one-resistor (1T1R) array with InGaZnOx field-effect transistor (IGZO-FET) and resistive random-access memory (RRAM) for analog CIM. The 3rd layer comprises multiple IGZO-FET-based photosensor arrays for wavelength-dependent optical sensing. The structural integrity and function of each layer are comprehensively verified. Furthermore, NSC is implemented using the M3D-SAIL architecture for a typical video keyframe-extraction task, achieving a high classification accuracy of 96.7% as well as a 31.5× lower energy consumption and 1.91× faster computing speed compared to its 2D counterpart.

Giant Electroresistance in Ferroionic Tunnel Junctions.

Oxide-based resistive switching devices, including ferroelectric tunnel junctions and resistance random access memory, are promising candidates for the next-generation non-volatile memory technology. In this work, we propose a ferroionic tunnel junction to realize a giant electroresistance. It functions as a ferroelectric tunnel junction at low resistance state and as a Schottky junction at high resistance state, due to interface engineering through the field-induced migration of oxygen vacancies. An extremely large electroresistance with ON/OFF ratios of 5.1×107 at room temperature and 2.1×109 at 10 K is achieved, using an ultrathin BaTiO3-δ layer as the ferroelectric barrier and a semiconducting Nb-doped SrTiO3 substrate as the bottom electrode. The results point toward an appealing way for the design of high-performance resistive switching devices based on ultrathin oxide heterostructures by ionic controlled interface engineering.

Artificial Synapses Emulated by an Electrolyte-Gated Tungsten-Oxide Transistor.

Considering that the human brain uses ≈1015 synapses to operate, the development of effective artificial synapses is essential to build brain-inspired computing systems. In biological synapses, the voltage-gated ion channels are very important for regulating the action-potential firing. Here, an electrolyte-gated transistor using WO3 with a unique tunnel structure, which can emulate the ionic modulation process of biological synapses, is proposed. The transistor successfully realizes synaptic functions of both short-term and long-term plasticity. Short-term plasticity is mimicked with the help of electrolyte ion dynamics under low electrical bias, whereas the long-term plasticity is realized using proton insertion in WO3 under high electrical bias. This is a new working approach to control the transition from short-term memory to long-term memory using different gate voltage amplitude for artificial synapses. Other essential synaptic behaviors, such as paired pulse facilitation, the depression and potentiation of synaptic weight, as well as spike-timing-dependent plasticity are also implemented in this artificial synapse. These results provide a new recipe for designing synaptic electrolyte-gated transistors through the electrostatic and electrochemical effects.