Heterogeneous density-based clustering with a dual-functional memristive array.

In the big data era, the requirement for data clustering methods that can handle massive and heterogeneous datasets with varying distributions increases. This study proposes a clustering algorithm for data sets with heterogeneous density using a dual-mode memristor crossbar array for data clustering. The array consists of a Ta/HfO2/RuO2 memristor operating in analog or digital modes, controlled by the reset voltage. The digital mode shows low dispersion and a high resistance ratio, and the analog mode enables precise conductance tuning. The local outlier factor is introduced to handle a heterogeneous density, and the required Euclidean and K-distances within the given dataset are calculated in the analog mode in parallel. In the digital mode, clustering is performed based on the connectivity among data points after excluding the detected outliers. The proposed algorithm boasts linear time complexity for the entire process. Extensive evaluations of synthetic datasets demonstrate significant improvement over representative density-based algorithms, and the datasets with heterogeneous density are clustered feasibly. Finally, the proposed algorithm is used to cluster the single-molecule localization microscopy data, demonstrating the feasibility of the suggested method for real-world problems.

Memristors with Tunable Volatility for Reconfigurable Neuromorphic Computing.

Neuromorphic computing promises an energy-efficient alternative to traditional digital processors in handling data-heavy tasks, primarily driven by the development of both volatile (neuronal) and nonvolatile (synaptic) resistive switches or memristors. However, despite their energy efficiency, memristor-based technologies presently lack functional tunability, thus limiting their competitiveness with arbitrarily programmable (general purpose) digital computers. This work introduces a two-terminal bilayer memristor, which can be tuned among neuronal, synaptic, and hybrid behaviors. The varying behaviors are accessed via facile control over the filament formed within the memristor, enabled by the interplay between the two active ionic species (oxygen vacancies and metal cations). This solution is unlike single-species ion migration employed in most other memristors, which makes their behavior difficult to control. By reconfiguring a single crossbar array of hybrid memristors, two different applications that usually require distinct types of devices are demonstrated - reprogrammable heterogeneous reservoir computing and arbitrary non-Euclidean graph networks. Thus, this work outlines a potential path toward functionally reconfigurable postdigital computers.

Memristive Crossbar Array-Based Probabilistic Graph Modeling.

Modern graph datasets with structural complexity and uncertainties due to incomplete information or data variability require advanced modeling techniques beyond conventional graph models. This study introduces a memristive crossbar array (CBA)-based probabilistic graph model (C-PGM) utilizing Cu0.3Te0.7/HfO2/Pt memristors, which exhibit probabilistic switching, self-rectifying, and memory characteristics. C-PGM addresses the complexities and uncertainties inherent in structural graph data across various domains, leveraging the probabilistic nature of memristors. C-PGM relies on the device-to-device variation across multiple memristive CBAs, overcoming the limitations of previous approaches that rely on sequential operations, which are slower and have a reliability concern due to repeated switching. This new approach enables the fast processing and massive implementation of probabilistic units at the expense of chip area. In this study, the hardware-based C-PGM feasibly expresses small-scale probabilistic graphs and shows minimal error in aggregate probability calculations. The probability calculation capabilities of C-PGM are applied to steady-state estimation and the PageRank algorithm, which is implemented on a simulated large-scale C-PGM. The C-PGM-based steady-state estimation and PageRank algorithm demonstrate comparable accuracy to conventional methods while significantly reducing computational costs.

Implementation of Bayesian networks and Bayesian inference using a Cu0.1Te0.9/HfO2/Pt threshold switching memristor.

Bayesian networks and Bayesian inference, which forecast uncertain causal relationships within a stochastic framework, are used in various artificial intelligence applications. However, implementing hardware circuits for the Bayesian inference has shortcomings regarding device performance and circuit complexity. This work proposed a Bayesian network and inference circuit using a Cu0.1Te0.9/HfO2/Pt volatile memristor, a probabilistic bit neuron that can control the probability of being 'true' or 'false.' Nodal probabilities within the network are feasibly sampled with low errors, even with the device's cycle-to-cycle variations. Furthermore, Bayesian inference of all conditional probabilities within the network is implemented with low power (<186 nW) and energy consumption (441.4 fJ), and a normalized mean squared error of ∼7.5 × 10-4 through division feedback logic with a variational learning rate to suppress the inherent variation of the memristor. The suggested memristor-based Bayesian network shows the potential to replace the conventional complementary metal oxide semiconductor-based Bayesian estimation method with power efficiency using a stochastic computing method.

Introduction to memristors and neuromorphic systems.

Recent generative artificial intelligence (AI) has exerted a profound and far-reaching global impact across diverse fields and society. However, it comes at the cost of substantial energy and computational resource consumption. Neuromorphic computing endeavors to create highly efficient computing hardware that emulates biological neural networks and even mimics some human brain functions, and it is expected to play an essential role in the next-generation computing hardware. Memristors open up novel opportunities for neuromorphic computing due to their feasible ability to mimic neural functions. Innovation in memristors may lead to novel algorithms and contribute to conventionally challenging tasks like nondeterministic polynomial time (NP)-hard problem. To this end, we present a themed collection in Materials Horizons and Nanoscale Horizons, in which we publish the latest developments in memristive materials, device fabrication, characterization, and circuit design for neuromorphic systems.

Tunable stochastic memristors for energy-efficient encryption and computing.

Information security and computing, two critical technological challenges for post-digital computation, pose opposing requirements - security (encryption) requires a source of unpredictability, while computing generally requires predictability. Each of these contrasting requirements presently necessitates distinct conventional Si-based hardware units with power-hungry overheads. This work demonstrates Cu0.3Te0.7/HfO2 ('CuTeHO') ion-migration-driven memristors that satisfy the contrasting requirements. Under specific operating biases, CuTeHO memristors generate truly random and physically unclonable functions, while under other biases, they perform universal Boolean logic. Using these computing primitives, this work experimentally demonstrates a single system that performs cryptographic key generation, universal Boolean logic operations, and encryption/decryption. Circuit-based calculations reveal the energy and latency advantages of the CuTeHO memristors in these operations. This work illustrates the functional flexibility of memristors in implementing operations with varying component-level requirements.

Study of a charge transition-driven resistive switching mechanism in TiO2-based random access memory via density functional theory.

The nature of the conducting filament (CF) with a high concentration of oxygen vacancies (VOs) in oxide thin film-based resistive random access memory (RRAM) remains unclear. The VOs in the CF have been assumed to be positively charged (VO2+) to explain the field-driven switching of RRAM, but VO2+ clusters in high concentration encounter Coulomb repulsion, rendering the CF unstable. Therefore, this study examined the oxidation state of VOs in the CF and their effects on the switching behavior via density functional theory calculations using a Pt/TiO2/Ti model system. It was concluded that the VOs in the CF are in a low oxidation state but are transformed to VO2+ immediately after release from the CF. In addition, the short-range interactions between VOs were confirmed to facilitate the rupture and rejuvenation of the CF by reducing the required activation energy. Finally, an improved switching model was proposed by considering the charge transition of VOs, providing a plausible explanation for the reported coexistence of two opposite bipolar switching polarities: the eight-wise and the counter-eight-wise polarities.

Multiphase Reset Induced Reliable Dual-Mode Resistance Switching of the Ta/HfO2/RuO2 Memristor.

Higher functionality should be achieved within the device-level switching characteristics to secure the operational possibility of mixed-signal data processing within a memristive crossbar array. This work investigated electroforming-free Ta/HfO2/RuO2 resistive switching devices for digital- and analog-type applications through various structural and electrical analyses. The multiphase reset behavior, induced by the conducting filament modulation and oxygen vacancy generation (annihilation) in the HfO2 layer by interacting with the Ta (RuO2) electrode, was utilized for the switching mode change. Therefore, a single device can manifest stable binary switching between low and high resistance states for the digital mode and the precise 8-bit conductance modulation (256 resistance values) via an optimized pulse application for the analog mode. An in-depth analysis of the operation in different modes and comparing memristors with different electrode structures validate the proposed mechanism. The Ta/HfO2/RuO2 resistive switching device is feasible for a mixed-signal processable memristive array.

Vertically Stackable Ovonic Threshold Switch Oscillator Using Atomic Layer Deposited Ge0.6Se0.4 Film for High-Density Artificial Neural Networks.

Nanodevice oscillators (nano-oscillators) have received considerable attention to implement in neuromorphic computing as hardware because they can significantly improve the device integration density and energy efficiency compared to complementary metal oxide semiconductor circuit-based oscillators. This work demonstrates vertically stackable nano-oscillators using an ovonic threshold switch (OTS) for high-density neuromorphic hardware. A vertically stackable Ge0.6Se0.4 OTS-oscillator (VOTS-OSC) is fabricated with a vertical crossbar array structure by growing Ge0.6Se0.4 film conformally on a contact hole structure using atomic layer deposition. The VOTS-OSC can be vertically integrated onto peripheral circuits without causing thermal damage because the fabrication temperature is <400 °C. The fabricated device exhibits oscillation characteristics, which can serve as leaky integrate-and-fire neurons in spiking neural networks (SNNs) and coupled oscillators in oscillatory neural networks (ONNs). For practical applications, pattern recognition and vertex coloring are demonstrated with SNNs and ONNs, respectively, using semiempirical simulations. This structure increases the oscillator integration density significantly, enabling complex tasks with a large number of oscillators. Moreover, it can enhance the computational speed of neural networks due to its rapid switching speed.

2Memristor-1Capacitor Integrated Temporal Kernel for High-Dimensional Data Mapping.

Compact but precise feature-extracting ability is core to processing complex computational tasks in neuromorphic hardware. Physical reservoir computing (RC) offers a robust framework to map temporal data into a high-dimensional space using the time dynamics of a material system, such as a volatile memristor. However, conventional physical RC systems have limited dynamics for the given material properties, restricting the methods to increase their dimensionality. This study proposes an integrated temporal kernel composed of a 2-memristor and 1-capacitor (2M1C) using a W/HfO2/TiN memristor and TiN/ZrO2/Al2O3/ZrO2/TiN capacitor to achieve higher dimensionality and tunable dynamics. The kernel elements are carefully designed and fabricated into an integrated array, of which performances are evaluated under diverse conditions. By optimizing the time dynamics of the 2M1C kernel, each memristor simultaneously extracts complementary information from input signals. The MNIST benchmark digit classification task achieves a high accuracy of 94.3% with a (196×10) single-layer network. Analog input mapping ability is tested with a Mackey-Glass time series prediction, and the system records a normalized root mean square error of 0.04 with a 20×1 readout network, the smallest readout network ever used for Mackey-Glass prediction in RC. These performances demonstrate its high potential for efficient temporal data analysis.

Heterogeneous reservoir computing in second-order Ta2O5/HfO2 memristors.

Multiple switching modes in a Ta2O5/HfO2 memristor are studied experimentally and numerically through a reservoir computing (RC) simulation to reveal the importance of nonlinearity and heterogeneity in the RC framework. Unlike most studies, where homogeneous reservoirs are used, heterogeneity is introduced by combining different behaviors of the memristor units. The chosen memristor for the reservoir units is based on a Ta2O5/HfO2 bilayer, in which the conductances of the Ta2O5 and HfO2 layers are controlled by the oxygen vacancies and deep/shallow traps, respectively, providing both volatile and non-volatile resistive switching modes. These several control parameters make the second-order Ta2O5/HfO2 memristor system present different behaviors in agreement with its history-dependent conductance and allow the fine-tuning of the behavior of each reservoir unit. The heterogeneity in the reservoir units improves the pattern recognition performance in the heterogeneous memristor RC system with a similar physical structure.

A high-dimensional in-sensor reservoir computing system with optoelectronic memristors for high-performance neuromorphic machine vision.

In-sensor reservoir computing (RC) is a promising technology to reduce power consumption and training costs of machine vision systems by processing optical signals temporally. This study demonstrates a high-dimensional in-sensor RC system with optoelectronic memristors to enhance the performance of the in-sensor RC system. Because optoelectronic memristors can respond to both optical and electrical stimuli, optical and electrical masks are proposed to improve the dimensionality and performance of the in-sensor RC system. An optical mask is employed to regulate the wavelength of light, while an electrical mask is used to control the initial conductance of zinc oxide optoelectronic memristors. The distinct characteristics of these two masks contribute to the representation of various distinguishable reservoir states, making it possible to implement diverse reservoir configurations with minimal correlation and to increase the dimensionality of the in-sensor RC system. Using the high-dimensional in-sensor RC system, handwritten digits are successfully classified with an accuracy of 94.1%. Furthermore, human action pattern recognition is achieved with a high accuracy of 99.4%. These high accuracies are achieved with the use of a single-layer readout network, which can significantly reduce the network size and training costs.

Spatiotemporal Data Processing with Memristor Crossbar-Array-Based Graph Reservoir.

Memristor-based physical reservoir computing (RC) is a robust framework for processing complex spatiotemporal data parallelly. However, conventional memristor-based reservoirs cannot capture the spatial relationship between the time-varying inputs due to the specific mapping scheme assigning one input signal to one memristor conductance. Here, a physical "graph reservoir" is introduced using a metal cell at the diagonal-crossbar array (mCBA) with dynamic self-rectifying memristors. Input and inverted input signals are applied to the word and bit lines of the mCBA, respectively, storing the correlation information between input signals in the memristors. In this way, the mCBA graph reservoirs can map the spatiotemporal correlation of the input data in a high-dimensional feature space. The high-dimensional mapping characteristics of the graph reservoir achieve notable results, including a normalized root-mean-square error of 0.09 in Mackey-Glass time series prediction, a 97.21% accuracy in MNIST recognition, and an 80.0% diagnostic accuracy in human connectome classification.

Cross-Wired Memristive Crossbar Array for Effective Graph Data Analysis.

Graphs adequately represent the enormous interconnections among numerous entities in big data, incurring high computational costs in analyzing them with conventional hardware. Physical graph representation (PGR) is an approach that replicates the graph within a physical system, allowing for efficient analysis. This study introduces a cross-wired crossbar array (cwCBA), uniquely connecting diagonal and non-diagonal components in a CBA by a cross-wiring process. The cross-wired diagonal cells enable cwCBA to achieve precise PGR and dynamic node state control. For this purpose, a cwCBA is fabricated using Pt/Ta2O5/HfO2/TiN (PTHT) memristor with high on/off and self-rectifying characteristics. The structural and device benefits of PTHT cwCBA for enhanced PGR precision are highlighted, and the practical efficacy is demonstrated for two applications. First, it executes a dynamic path-finding algorithm, identifying the shortest paths in a dynamic graph. PTHT cwCBA shows a more accurate inferred distance and ≈1/3800 lower processing complexity than the conventional method. Second, it analyzes the protein-protein interaction (PPI) networks containing self-interacting proteins, which possess intricate characteristics compared to typical graphs. The PPI prediction results exhibit an average of 30.5% and 21.3% improvement in area under the curve and F1-score, respectively, compared to existing algorithms.

Impact of operation voltage and NH3 annealing on the fatigue characteristics of ferroelectric AlScN thin films grown by sputtering.

This work investigates the impact of the magnitude of cycling voltage on the fatigue characteristics of 40 nm-thick AlScN ferroelectric thin film. The fatigue rate and the rejuvenation of remanent polarization vary with the cycling voltage. The primary fatigue mechanism is identified to be the interfacial layer formation and domain wall pinning at high and low cycling voltages, respectively. Additionally, annealing the film under the NH3 atmosphere decreases the fatigue rate and improves endurance by eliminating impurities in the film. The amount of trapped charges at the interface also decreases after NH3 annealing, leading to a reduction in leakage current. Furthermore, the ferroelectric performance of the AlScN film is not degraded after the thermal annealing at 900 °C under the NH3 environment, suggesting its robustness against the severe thermal budget. It is concluded that NH3 annealing is a promising method to address the reliability issue of the AlScN film.

Highly parallel stateful Boolean logic gates based on aluminum-doped self-rectifying memristors in a vertical crossbar array structure.

The self-rectifying memristor with electronic bipolar resistive switching shows electroforming-free, highly rectifying properties and low operating power. Furthermore, configuring the memristors in a vertical array structure provides a higher memory density than in a planar array structure. These combined advantages can be exploited in in-memory computing, which may provide a new and efficient stateful logic gate with high parallelism compared to the conventional stateful logic gates in the planar array structure. The different switching mechanism compared to the previous logic gates based on filamentary-type switching is explained and exploited to realize the AND and OR Boolean logic gates. Since the AND and OR logic functions are the basic operations of sum-of-product (SoP) and product-of-sum (PoS) expressions, any canonical expression for Boolean logic can be implemented in the vertical crossbar array (CBA). Accordingly, the composite logic gate, such as an exclusive OR operation, is demonstrated. In addition, the implementation of the memristive priority encoder is proposed using parallel logic gates. Although the switching speed should be improved in further work, a higher parallelism with a larger number of layers in the vertical array structure can mitigate the low operation speed issue.

Review of Semiconductor Flash Memory Devices for Material and Process Issues.

Vertically integrated NAND (V-NAND) flash memory is the main data storage in modern handheld electronic devices, widening its share even in the data centers where installation and operation costs are critical. While the conventional scaling rule has been applied down to the design rule of ≈15 nm (year 2013), the current method of increasing device density is stacking up layers. Currently, 176-layer-stacked V-NAND flash memory is available on the market. Nonetheless, increasing the layers invokes several challenges, such as film stress management and deep contact hole etching. Also, there should be an upper bound for the attainable stacking layers (400-500) due to the total allowable chip thickness, which will be reached within 6-7 years. This review summarizes the current status and critical challenges of charge-trap-based flash memory devices, with a focus on the material (floating-gate vs charge-trap-layer), array-level circuit architecture (NOR vs NAND), physical integration structure (2D vs 3D), and cell-level programming technique (single vs multiple levels). Current efforts to improve fabrication processes and device performances using new materials are also introduced. The review suggests directions for future storage devices based on the ionic mechanism, which may overcome the inherent problems of flash memory devices.

Graph Analysis with Multifunctional Self-Rectifying Memristive Crossbar Array.

Many big data have interconnected and dynamic graph structures growing over time. Analyzing these graphical data requires the hidden relationship between the nodes in the graphs to be identified, which has conventionally been achieved by finding the effective similarity. However, graphs are generally non-Euclidean, which does not allow finding it. In this study, the non-Euclidean graphs are mapped to a specific crossbar array (CBA) composed of self-rectifying memristors and metal cells at the diagonal positions. The sneak current, an intrinsic physical property in the CBA, allows for the identification of the similarity function. The sneak-current-based similarity function indicates the distance between the nodes, which can be used to predict the probability that unconnected nodes will be connected in the future, connectivity between communities, and neural connections in a brain. When all bit lines of the CBA are connected to the ground, the sneak current is suppressed, and the CBA can be used to search for adjacent nodes. This work demonstrates the physical calculation methods applied to various graphical problems using the CBA composed of the self-rectifying memristor based on the HfO2 switching layer. Moreover, such applications suffer less from the memristors' inherent issues related to their stochastic nature.

Atomic Layer Deposition of Sb2 Te3 /GeTe Superlattice Film and Its Melt-Quenching-Free Phase-Transition Mechanism for Phase-Change Memory.

Atomic layer deposition (ALD) of Sb2 Te3 /GeTe superlattice (SL) film on planar and vertical sidewall areas containing TiN metal and SiO2 insulator is demonstrated. The peculiar chemical affinity of the ALD precursor to the substrate surface and the 2D nature of the Sb2 Te3 enable the growth of an in situ crystallized SL film with a preferred orientation. The SL film shows a reduced reset current of ≈1/7 of the randomly oriented Ge2 Sb2 Te5 alloy. The reset switching is induced by the transition from the SL to the (111)-oriented face-centered-cubic (FCC) Ge2 Sb2 Te5 alloy and subsequent melt-quenching-free amorphization. The in-plane compressive stress, induced by the SL-to-FCC structural transition, enhances the electromigration of Ge along the [111] direction of FCC structure, which enables such a significant improvement. Set operation switches the amorphous to the (111)-oriented FCC structure.

Probabilistic computing using Cu0.1Te0.9/HfO2/Pt diffusive memristors.

A computing scheme that can solve complex tasks is necessary as the big data field proliferates. Probabilistic computing (p-computing) paves the way to efficiently handle problems based on stochastic units called probabilistic bits (p-bits). This study proposes p-computing based on the threshold switching (TS) behavior of a Cu0.1Te0.9/HfO2/Pt (CTHP) diffusive memristor. The theoretical background of the p-computing resembling the Hopfield network structure is introduced to explain the p-computing system. P-bits are realized by the stochastic TS behavior of CTHP diffusive memristors, and they are connected to form the p-computing network. The memristor-based p-bit is likely to be '0' and '1', of which probability is controlled by an input voltage. The memristor-based p-computing enables all 16 Boolean logic operations in both forward and inverted operations, showing the possibility of expanding its uses for complex operations, such as full adder and factorization.