Demonstration of a low power and high-speed graphene/silicon heterojunction near-infrared photodetector.

The structure and process of the graphene/Si heterojunction near-infrared photodetector were optimized to enhance the operating speed limit. The introduction of a well-designed structure improved the rise time from 12.6 µs to 115 ns, albeit at the expense of the responsivity, which decreased from 1.25 A W-1 to 0.56 A W-1. Similarly, the falling time was improved from 38 µs to 288 ns with a sacrifice in responsivity from 1.25 A W-1 to 0.29 A W-1, achieved through the introduction of Ge-induced defect-recombination centers within the well. Through a judicious well design and the introduction of recombination defect centers, the minimum pulse width could be improved from 50.6 µs to 435 ns, facilitating 2 MHz operation. This represents more than 100 times increase compared to previously reported graphene and graphene/Si hybrid photodetectors.

Reconfigurable Single-Layer Graphene Radio Frequency Antenna Device Capable of Changing Resonant Frequency.

A reconfigurable passive device that can manipulate its resonant frequency by controlling its quantum capacitance value without requiring complicated equipment has been experimentally investigated by modifying the Fermi level of large-area graphene using an external electric field. When the total capacitance change, caused by the gate bias in the passive graphene device, was increased to 60% compared to the initial state, a 6% shift in the resonant frequency could be achieved. While the signal characteristics of the graphene antenna are somewhat inferior compared to the conventional metal antenna, simplifying the device structure allowed reconfigurable characteristics to be implemented by using only the gate bias change.

Demonstration of p-type stack-channel ternary logic device using scalable DNTT patterning process.

A p-type ternary logic device with a stack-channel structure is demonstrated using an organic p-type semiconductor, dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT). A photolithography-based patterning process is developed to fabricate scaled electronic devices with complex organic semiconductor channel structures. Two layers of thin DNTT with a separation layer are fabricated via the low-temperature deposition process, and for the first time, p-type ternary logic switching characteristics exhibiting zero differential conductance in the intermediate current state are demonstrated. The stability of the DNTT stack-channel ternary logic switch device is confirmed by implementing a resistive-load ternary logic inverter circuit.

Dual-channel P-type ternary DNTT-graphene barristor.

P-type ternary switch devices are crucial elements for the practical implementation of complementary ternary circuits. This report demonstrates a p-type ternary device showing three distinct electrical output states with controllable threshold voltage values using a dual-channel dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]-thiophene-graphene barristor structure. To obtain transfer characteristics with distinctively separated ternary states, novel structures called contact-resistive and contact-doping layers were developed. The feasibility of a complementary standard ternary inverter design around 1 V was demonstrated using the experimentally calibrated ternary device model.

Demonstration of Anti-ambipolar Switch and Its Applications for Extremely Low Power Ternary Logic Circuits.

Anti-ambipolar switch (AAS) devices at a narrow bias region are necessary to solve the intrinsic leakage current problem of ternary logic circuits. In this study, an AAS device with a very high peak-to-valley ratio (∼106) and adjustable operating range characteristics was successfully demonstrated using a ZnO and dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene heterojunction structure. The entire device integration was completed at a low thermal budget of less than 200 °C, which makes this AAS device compatible with monolithic 3D integration. A 1-trit ternary full adder designed with this AAS device exhibits excellent power-delay product performance (∼122 aJ) with extremely low power (∼0.15 µW, 7 times lower than the reference circuit) and lower device count than those of other ternary device candidates.

Performance Degradation in Graphene-ZnO Barristors Due to Graphene Edge Contact.

The physical and chemical characteristics of the edge states of graphene have been studied extensively as they affect the electrical properties of graphene significantly. Likewise, the edge states of graphene in contact with semiconductors or transition-metal dichalcogenides (TMDs) are expected to have a strong influence on the electrical properties of the resulting Schottky junction devices. We found that the edge states of graphene form chemical bonds with the ZnO layer, which limits the modulation of the Fermi level at the graphene-semiconductor junction, in a manner similar to Fermi level pinning in silicon devices. Therefore, we propose that graphene-based Schottky contact should be accomplished with minimal edge contact to reduce the limits imposed on the Fermi level modulation; this hypothesis has been experimentally verified, and its microscopic mechanism is further theoretically examined.

Channel Defect Profiling and Passivation for ZnO Thin-Film Transistors.

The electrical characteristics of Zinc oxide (ZnO) thin-film transistors are analyzed to apprehend the effects of oxygen vacancies after vacuum treatment. The energy level of the oxygen vacancies was found to be located near the conduction band of ZnO, which contributed to the increase in drain current (ID) via trap-assisted tunneling when the gate voltage (VG) is lower than the specific voltage associated with the trap level. The oxygen vacancies were successfully passivated after the annealing of ZnO in oxygen ambient. We determined that the trap-induced Schottky barrier lowering reduced a drain barrier when the drain was subjected to negative bias stress. Consequentially, the field effect mobility increased from 8.5 m2 V-1·s-1 to 8.9 m2 V-1·s-1 and on-current increased by ~13%.

A negative electrocaloric effect in an antiferroelectric zirconium dioxide thin film.

A large negative electrocaloric effect is demonstrated in an antiferroelectric ZrO2 thin film with 8 nm thickness deposited by atomic layer deposition. An adiabatic temperature change as high as ΔT = -31 K is obtained for an electric field change of ΔE = 3.45 MV cm-1 at an ambient temperature of 413 K. Moreover, the ZrO2 thin film shows enhanced stability as demonstrated by endurance and Preisach density maps. Due to its high phase transition temperature, high thermal stability, high scalability and full CMOS compatibility, ZrO2 is proposed as a promising candidate for future multilayer electrocaloric and solid-state cooling devices.

Operation Mechanism of a MoS2/BP Heterojunction FET.

The electrical characteristics and operation mechanism of a molybdenum disulfide/black phosphorus (MoS2/BP) heterojunction device are investigated herein. Even though this device showed a high on-off ratio of over 1 × 107, with a lower subthreshold swing of ~54 mV/dec and a 1fA level off current, its operating mechanism is closer to a junction field-effect transistor (FET) than a tunneling FET. The off-current of this device is governed by the depletion region in the BP layer, and the band-to-band tunneling current does not contribute to the rapid turn-on and extremely low off-current.

A graphene barristor using nitrogen profile controlled ZnO Schottky contacts.

We have successfully demonstrated a graphene-ZnO:N Schottky barristor. The barrier height between graphene and ZnO:N could be modulated by a buried gate electrode in the range of 0.5-0.73 eV, and an on-off ratio of up to 107 was achieved. By using a nitrogen-doped ZnO film as a Schottky contact material, the stability problem of previously reported graphene barristors could be greatly alleviated and a facile route to build a top-down processed graphene barristor was realized with a very low heat cycle. This device will be instrumental when implementing logic functions in systems requiring high-performance logic devices fabricated with a low temperature fabrication process such as back-end integrated logic devices or flexible devices on soft substrates.

Characteristics of a pressure sensitive touch sensor using a piezoelectric PVDF-TrFE/MoS2 stack.

A new touch sensor device has been demonstrated with molybdenum disulfide (MoS2) field effect transistors stacked with a piezoelectric polymer, polyvinylidene fluoride-trifluoroethylene (PVDF-TrFE). The performance of two device stack structures, metal/PVDF-TrFE/MoS2 (MPM) and metal/PVDF-TrFE/Al2O3/MoS2 (MPAM), were compared as a function of the thickness of PVDF-TrFE and Al2O3. The sensitivity of the touch sensor has been improved by two orders of magnitude by reducing the charge scattering and enhancing the passivation effects using a thin Al2O3 interfacial layer. Reliable switching behavior has been demonstrated up to 120 touch press cycles.

Ferroelectric polymer-gated graphene memory with high speed conductivity modulation.

The feasibility of a high speed ferroelectric graphene memory device using a ferroelectric polymer (PVDF-TrFE)/graphene stack has been demonstrated. The conductivity of this metal-ferroelectric-graphene (MFG) device could be modulated up to 775% with a very fast programming speed down to 10 ns. Also, programmed states were maintained up to 1000 s with endurance over 1000 cycles. In addition to demonstrating a single memory device, the array-level integration and cell write/read functionality of a 4 × 4 MFG array adopting a graphene bit line has also been confirmed to show the feasibility of MFG memory.

Effects of multi-layer graphene capping on Cu interconnects.

The benefits of multi-layer graphene (MLG) capping on Cu interconnects have been experimentally demonstrated. The resistance of MLG capped Cu wires improved by 2-7% compared to Cu wires. The breakdown current density increased by 18%, suggesting that the MLG can act as an excellent capping material for Cu interconnects, improving the reliability characteristics. With a proper process optimization, MLG capped Cu interconnects could become a promising technology for high density back end-of-line interconnects.

Characteristics of CVD graphene nanoribbon formed by a ZnO nanowire hardmask.

A graphene nanoribbon (GNR) is an important basic structure to open a bandgap in graphene. The GNR processes reported in the literature are complex, time-consuming, and expensive; moreover, the device yield is relatively low. In this paper, a simple new process to fabricate a long and straight graphene nanoribbon with a high yield has been proposed. This process utilizes CVD graphene substrate and a ZnO nanowire as the hardmask for patterning. 8 µm long and 50-100 nm wide GNRs were successfully demonstrated in high density without any trimming, and ∼ 10% device yield was realized with a top-down patterning process. After passivating the surfaces of the GNRs using a low temperature atomic layer deposition (ALD) of Al(2)O(3), high performance GNR MOSFETs with symmetric drain-current-gate-voltage (I(d)-V(g)) curves were demonstrated and a field effect mobility up to ∼ 1200 cm(2) V(-1) s(-1) was achieved at V(d) = 10 mV.