Poly(styrene)-block-Maltoheptaose Films for Sub-10 nm Pattern Transfer: Implications for Transistor Fabrication.

Sequential infiltration synthesis (SIS) into poly(styrene)-block-maltoheptaose (PS-b-MH) block copolymer using vapors of trimethyl aluminum and water was used to prepare nanostructured surface layers. Prior to the infiltration, the PS-b-MH had been self-assembled into 12 nm pattern periodicity. Scanning electron microscopy indicated that horizontal alumina-like cylinders of 4.9 nm diameter were formed after eight infiltration cycles, while vertical cylinders were 1.3 nm larger. Using homopolymer hydroxyl-terminated poly(styrene) (PS-OH) and MH films, specular neutron reflectometry revealed a preferential reaction of precursors in the MH compared to PS-OH. The infiltration depth into the maltoheptaose homopolymer film was found to be 2.0 nm after the first couple of cycles. It reached 2.5 nm after eight infiltration cycles, and the alumina incorporation within this infiltrated layer corresponded to 23 vol % Al2O3. The alumina-like material, resulting from PS-b-MH infiltration, was used as an etch mask to transfer the sub-10 nm pattern into the underlying silicon substrate, to an aspect ratio of approximately 2:1. These results demonstrate the potential of exploiting SIS into carbohydrate-based polymers for nanofabrication and high pattern density applications, such as transistor devices.

Template-assisted vapour-liquid-solid growth of InP nanowires on (001) InP and Si substrates.

We report on the synthesis of vertical InP nanowire arrays on (001) InP and Si substrates using template-assisted vapour-liquid-solid growth. A thick silicon oxide layer was first deposited on the substrates. The samples were then patterned by electron beam lithography and deep dry etching through the oxide layer down to the substrate surface. Gold seed particles were subsequently deposited in the holes of the pattern by the use of pulse electrodeposition. The subsequent growth of nanowires by the vapour-liquid-solid method was guided towards the [001] direction by the patterned oxide template, and displayed a high growth yield with respect to the array of holes in the template. In order to confirm the versatility and robustness of the process, we have also demonstrated guided growth of InP nanowire p-n junctions and InP/InAs/InP nanowire heterostructures on (001) InP substrates. Our results show a promising route to monolithically integrate III-V nanowire heterostructure devices with commercially viable (001) silicon platforms.

III-V nanowire synthesis by use of electrodeposited gold particles.

Semiconductor nanowires are great candidates for building novel electronic devices. Considering the cost of fabricating such devices, substrate reuse and gold consumption are the main concerns. Here we report on implementation of high throughput gold electrodeposition for selective deposition of metal seed particles in arrays defined by lithography for nanowire synthesis. By use of this method, a reduction in gold consumption by a factor of at least 300 was achieved, as compared to conventional thermal evaporation for the same pattern. Because this method also facilitates substrate reuse, a significantly reduced cost of the final device is expected. We investigate the morphology, crystallography, and optical properties of InP and GaAs nanowires grown from electrodeposited gold seed particles and compare them with the properties of nanowires grown from seed particles defined by thermal evaporation of gold. We find that nanowire synthesis, as well as the material properties of the grown nanowires are comparable and quite independent of the gold deposition technique. On the basis of these results, electrodeposition is proposed as a key technology for large-scale fabrication of nanowire-based devices.