CMOS-compatible Hf0.5Zr0.5O2-based ferroelectric memory crosspoints fabricated with damascene process.

We report the fabrication of Hf0.5Zr0.5O2(HZO) based ferroelectric memory crosspoints using a CMOS-compatible damascene process. In this work, we compared 12 and 56 µm² crosspoint devices with the 0.02 mm² round devices commonly used as a benchmark. For all devices, a 9 nm thick ferroelectric thin film was deposited by plasma-enhanced atomic layer deposition (PEALD) on planarized bottom electrodes (BE). The wake-up appeared to be longer for the crosspoint memories compared to 0.02 mm² benchmark, while all the devices reached a 2Prvalue of ~ 50 µC/cm² after 105cycles with 3 V/10 µs squared pulses. The crosspoints stand out for their superior endurance, which was increased by an order of magnitude. Nucleation limited switching (NLS) experiments were performed, revealing a switching time < 170 ns for our 12 and 56 µm² devices, while it remained in the µs range for the larger round devices. The downscaled devices demonstrate notable advantages with a rise in endurance and switching speed.

CMOS Compatible Hydrogen Sensor Using Platinum Gate and ALD-Aluminum Oxide.

In this study, a p-Si/ALD-Al2O3/Ti/Pt MOS (metal oxide semiconductor) device has been fabricated and used as a hydrogen sensor. The use of such a stack enables a reliable, industry-compatible CMOS fabrication process. ALD-Al2O3 has been chosen as it can be integrated into the back end of the line (BEOL) or in CMOS, post processing. The device response and recovery are demonstrated with good correlation between the capacitance variation and the hydrogen concentration. Detection down to 20 ppm at 140 °C was obtained and a response time of 56 s for 500 ppm was recorded.

Wafer-scale detachable monocrystalline germanium nanomembranes for the growth of III-V materials and substrate reuse.

Germanium (Ge) is increasingly used as a substrate for high-performance optoelectronics, photovoltaics, and electronic devices. These devices are usually grown on thick and rigid Ge substrates manufactured by classical wafering techniques. Nanomembranes (NMs) provide an alternative to this approach while offering wafer-scale lateral dimensions, weight reduction, waste limitation, and cost effectiveness. Herein, we introduce the Porous germanium Efficient Epitaxial LayEr Release (PEELER) process, which consists of the fabrication of wafer-scale detachable Ge NMs on porous Ge (PGe) and substrate reuse. We demonstrate the growth of Ge NMs with monocrystalline quality as revealed by high-resolution transmission electron microscopy (HRTEM) characterization. Together with the surface roughness below 1 nm, it makes the Ge NMs suitable for growth of III-V materials. Additionally, the embedded nanoengineered weak layer enables the detachment of the Ge NMs. Finally, we demonstrate the wet-etch-reconditioning process of the Ge substrate, allowing its reuse, to produce multiple free-standing NMs from a single parent wafer. The PEELER process significantly reduces the consumption of Ge in the fabrication process, paving the way for a new generation of low-cost flexible optoelectronic devices.

Impact of III-Nitride/Si Interface Preconditioning on Breakdown Voltage in GaN-on-Silicon HEMT.

In this paper, an AIGaN/GaN metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT) device is realized. The device shows normal ON characteristics with a maximum current of 570 mA/mm at a gate-to-source voltage of 3 V, an on-state resistance of 7.3 Ω·mm and breakdown voltage of 500 V. The device has been modeled using numerical simulations to reproduce output and transfer characteristics. We identify, via experimental results and TCAD simulations, the main physical mechanisms responsible for the premature breakdown. The contribution of the AlN/Silicon substrate interface to the premature off-state breakdown is pointed out. Vertical leakage in lateral GaN devices significantly contributes to the off-state breakdown at high blocking voltages. The parasitic current path leads to premature breakdown before the appearance of avalanche or dielectric breakdown. A comparative study between a MOS-HEMT GaN on a silicon substrate with and without a SiNx interlayer at the AlN/Silicon substrate interface is presented here. We show that it is possible to increase the breakdown voltages of the fabricated transistors on a silicon substrate using SiNx interlayer.

Hybrid absorption/interference wide-angle filter using PECVD Si-Rich SixNy and SiOx for LED lighting.

We propose a method to fabricate interference filters using Plasma Enhanced Chemical Vapor Deposition (PECVD) to reduce blue and near-infrared wavelengths that are inherent to LED lighting, but that have a negative impact on human health and the environment respectively. We developed a Si-rich silicon nitride (Si-rich SixNy) material, with a very high refractive index, a high extinction coefficient in the blue range and a very low extinction coefficient in the rest of the spectrum. We combined this Si-rich SixNy with silicon oxide (SiOx) to realize an LED interference filter. The use of a material with a selective absorbance and high refractive index allows a simple fabrication process of the filter composed of six layers only, even for a complex spectral response. Moreover, the filter response is uniform and tolerant to incidence angle variation. With this work, we demonstrate the high potential of PECVD technique for the fabrication of low cost and reproducible interference filters that could be used in various applications.