Disturbance characteristics of half-selected cells in a cross-point resistive switching memory array.

Disturbance characteristics of cross-point resistive random access memory (RRAM) arrays are comprehensively studied in this paper. An analytical model is developed to quantify the number of pulses (#Pulse) the cell can bear before disturbance occurs under various sub-switching voltage stresses based on physical understanding. An evaluation methodology is proposed to assess the disturb behavior of half-selected (HS) cells in cross-point RRAM arrays by combining the analytical model and SPICE simulation. The characteristics of cross-point RRAM arrays such as energy consumption, reliable operating cycles and total error bits are evaluated by the methodology. A possible solution to mitigate disturbance is proposed.

Metal oxide-resistive memory using graphene-edge electrodes.

The emerging paradigm of 'abundant-data' computing requires real-time analytics on enormous quantities of data collected by a mushrooming network of sensors. Todays computing technology, however, cannot scale to satisfy such big data applications with the required throughput and energy efficiency. The next technology frontier will be monolithically integrated chips with three-dimensionally interleaved memory and logic for unprecedented data bandwidth with reduced energy consumption. In this work, we exploit the atomically thin nature of the graphene edge to assemble a resistive memory (∼ 3 Šthick) stacked in a vertical three-dimensional structure. We report some of the lowest power and energy consumption among the emerging non-volatile memories due to an extremely thin electrode with unique properties, low programming voltages, and low current. Circuit analysis of the three-dimensional architecture using experimentally measured device properties show higher storage potential for graphene devices compared that of metal based devices.

Experimental study of plane electrode thickness scaling for 3D vertical resistive random access memory.

The vertical scaling for the multi-layer stacked 3D vertical resistive random access memory (RRAM) cross-point array is investigated. The thickness of the multi-layer stack for a 3D RRAM is a key factor for determining the storage density. A vertical RRAM cell with plane electrode thickness (tm) scaled down to 5 nm, aiming to minimize 3D stack height, is experimentally demonstrated. An improvement factor of 5 in device density can be achieved as compared to a previous demonstration using a 22 nm thick plane electrode. It is projected that 37 layers can be stacked for a lithographic half-pitch (F) = 26 nm and total thickness of one stack (T) = 21 nm, delivering a bit density of 72.8 nm(2)/cell.