Low-Frequency Noise Characteristics in Multi-Layer WSe2 Field Effect Transistors with Different Contact Metals.

In this work, we analyze characteristics of Ohmic, Schottky forward and reverse contact through a low-frequency noise (LFN) measurement, combining two types of metals (Pd and Au) as the source and drain (S/D) contacts that enable p-type properties in multi-layer WSe2 field effect transistors (FETs). The LFN is one of the significant factors liming the performance of nano-scale devices such as TMDCs FETs having large surface-to-volume ratio. In addition, the LFN analysis, which relates to the device reliability, can help identify sensitive areas for current transport and evaluate the analog circuit applicability. Theoretically, the multi-layer WSe2 has reasonable electron affinity and bandgap that can make p-channel FET using the metal with a relatively high work-function. However, it is experimentally confirmed that Schottky contact characteristics are exhibited in the multi-layer WSe2 FETs with various metals except Pd due to the metal Fermi level pinning phenomenon. Mobility (µeff, ~87.5 cm²/V·s), one of the electrical performance extracted from fabricated devices with Pd as S/D electrodes shows a great difference from that (~0.572 cm²/V·s) of devices with Au as S/D electrodes. The measured electrical characteristics show that a Schottky contact is formed at an interface between Au and WSe2 causing the higher LFN of the FETs than that of device with Pd as S/D electrodes. This characteristic is also verified by confirming the reduction of LFN due to the decreased effect of the Schottky property as the drain bias is increased.

Emerging memory technologies for neuromorphic computing.

In this paper, we reviewed the recent trends on neuromorphic computing using emerging memory technologies. Two representative learning algorithms used to implement a hardware-based neural network are described as a bio-inspired learning algorithm and software-based learning algorithm, in particular back-propagation. The requirements of the synaptic device to apply each algorithm were analyzed. Then, we reviewed the research trends of synaptic devices to implement an artificial neural network.

A Split-Gate Positive Feedback Device With an Integrate-and-Fire Capability for a High-Density Low-Power Neuron Circuit.

Hardware-based spiking neural networks (SNNs) to mimic biological neurons have been reported. However, conventional neuron circuits in SNNs have a large area and high power consumption. In this work, a split-gate floating-body positive feedback (PF) device with a charge trapping capability is proposed as a new neuron device that imitates the integrate-and-fire function. Because of the PF characteristic, the subthreshold swing (SS) of the device is less than 0.04 mV/dec. The super-steep SS of the device leads to a low energy consumption of ∼0.25 pJ/spike for a neuron circuit (PF neuron) with the PF device, which is ∼100 times smaller than that of a conventional neuron circuit. The charge storage properties of the device mimic the integrate function of biological neurons without a large membrane capacitor, reducing the PF neuron area by about 17 times compared to that of a conventional neuron. We demonstrate the successful operation of a dense multiple PF neuron system with reset and lateral inhibition using a common self-controller in a neuron layer through simulation. With the multiple PF neuron system and the synapse array, on-line unsupervised pattern learning and recognition are successfully performed to demonstrate the feasibility of our PF device in a neural network.

Accurate extraction of WSe2 FETs parameters by using pulsed I-V method at various temperatures.

This work investigates the intrinsic characteristics of multilayer WSe2 field effect transistors (FETs) by analysing Pulsed I-V (PIV) and DC characteristics measured at various temperatures. In DC measurement, unwanted charge trapping due to the gate bias stress results in I-V curves different from the intrinsic characteristic. However, PIV reduces the effect of gate bias stress so that intrinsic characteristic of WSe2 FETs is obtained. The parameters such as hysteresis, field effect mobility (µeff), subthreshold slope (SS), and threshold voltage (Vth) measured by PIV are significantly different from those obtained by DC measurement. In PIV results, the hysteresis is considerably reduced compared with DC measurement, because the charge trapping effect is significantly reduced. With increasing temperature, the field effect mobility (µeff) and subthreshold swing (SS) are deteriorated, and threshold voltage (Vth) decreases.