Emission enhancement of InGaN/GaN light emitting diode by using Ag nanoparticles.

We have studied the effect of surface plasmon (SP) coupling to enhance emission efficiency of light emitting diode (LED) with multiple quantum wells (MQWs) structure by positioning Ag nanoparticles on the line-arrayed patterns. The line-arrayed patterns were fabricated by photolithography and inductively coupled plasma reactive ion etching process. The Ag nanoparticles were formed by thermal annealing at 300 degrees C and 400 degrees C for 30 min for Ag films with thickness of 10 nm and 15 nm deposited on the patterned LED structures, respectively. The photoluminescence (PL) emission intensity of line-patterned LED with Ag nanoparticles was overall enhanced. According to the spectra of time resolved PL, carrier life times of line-patterned LED with and without Ag nanoparticles appeared about 0.47 and 5.47 ns, respectively.

Structural properties of indium tin oxide thin films by glancing angle deposition method.

We have studied the structural and optical properties of indium tin oxide (ITO) films deposited on sapphire substrates by electron beam evaporator with glancing angle deposition method. The ITO films were grown with different deposition angles of 0 degrees, 30 degrees, 45 degrees, 60 degrees at fixed deposition rate of 3 angstroms/s and with deposition rates of 2 angstroms/s, 3 angstroms/s, and 4angstroms/s at deposition angle of 45 degrees, respectively. From analysis of ellipsometry measurements, it appears that the void fraction of the films increased and their refractive indices decreased from 2.18 to 1.38 at the wavelength of 500 as increasing the deposition angle. The refractive index in the wavelength ranges of 550 nm-800 nm also depends on the deposition rates. Transmittance of ITO film with 235-nm-thickness grown at 60 degrees was covered about 20-80%, and then it was increased in visible wavelength range with increase of deposition angle.

Resistive-switching memory effect of hybrid structures with polyimide and SnO2 nanocrystals.

Hybrid memory devices with polyimide and SnO2 nanocrystals on a flexible polyethersulphone substrate have shown a memristor behavior from current-voltage (I-V) measurements. The resistive-switching effects with a current bistability appeared during cycling voltage sweeping within the range of +/- 4 V. This I-V switching effect might have originated from a resistance fluctuation due to the charge trapping into the SnO2 nanocrystals as well as the oxygen vacancies of the ZnO layer and aluminum oxides that were formed between the polyimide and the interface of the Al gate electrode. In the bipolar resistance-switching behavior, the ratio of the high- and low-resistance state currents was about 3.7 x 10(4) at 1 V.

In2O3 nanocrystal memory with the barrier engineered tunnel layer.

In2O3 nanocrystal memories with barrier-engineered tunnel layers were fabricated on a p-type Si substrate. The structure and thickness of the barrier-engineered tunnel layers were SiO2/Si3N4/SiO2 (ONO) and 2/2/3 nm, respectively. The equivalent oxide thickness of the ONO tunnel layers was 5.64 nm. The average size and density of the In2O3 nanocrystals after the reaction between BPDA-PDA polyimide and the In thin film were about 8 nm and 4 x 10(11) cm(-2), respectively. The electrons were charged from the channel of the memory device to the quantum well of the In2O3 nanocrystal through the ONO tunnel layer via Fowler-Nordheim tunneling. The memory window was about 1.4 V when the program and erase conditions of the In2O3 nanocrystal memory device were 12 V for 1 s and -15 V for 200 ms.

Nonvolatile memory characteristics of WSi2 nanocrystals embedded in SiO2 dielectrics.

A nano-floating gate capacitor with WSi2 nanocrystals embedded in SiO2 dielectrics was fabricated. The WSi2 nanocrystals were created from ultrathin WSi2 film during rapid thermal annealing process and their average size and density were about 2.5 nm and 3.59 x 10(12) cm(-2), respectively. The flat-band voltage shift due to the carrier charging effect of WSi2 nanocrystals were measured up to 5.9 V when the gate voltage sweep in the range of +/- 9 V. The memory window was decreased from 3.7 V to 1.9 V after 1 h and remained about 3.7 V after 10(5) programming/erasing cycles. These results show that there is a possibility for the WSi2 nanocrystals to be applied to nonvolatile memory devices.

Thermal stability of metal-silicide nanocrystal nonvolatile memory with barrier engineered tunnel layers.

WSi2 nanocrystal nonvolatile memory devices were fabricated with a silicon oxide-nitride-oxide (SiO2: 2 nm/Si3N4:2 nm/SiO2:3 nm) tunnel layer. WSi2 nanocrystals of 2.5 nm diameters and a density of 3.6 x 10(12) cm(-2) were formed using radio frequency magnetron sputtering and annealing processes. The WSi2 nanocrystal nonvolatile memory device exhibited strong thermal stability during writing/erasing operations at temperatures up to 125 degrees C. When the writing/erasing voltages were applied at +10 V/-10 V for 500 ms, the memory window of the initial approximately 2.6 V decreased by approximately 1.1 V at 25 degrees C and 0.4 V at 125 degrees C after 10(4) sec, respectively. These results show that WSi2 nanocrystals with barrier-engineered tunnel layers are possible for application in nonvolatile memory devices.