Performance analysis of DNA crossbar arrays for high-density memory storage applications.

Deoxyribonucleic acid (DNA) has emerged as a promising building block for next-generation ultra-high density storage devices. Although DNA has high durability and extremely high density in nature, its potential as the basis of storage devices is currently hindered by limitations such as expensive and complex fabrication processes and time-consuming read-write operations. In this article, we propose the use of a DNA crossbar array architecture for an electrically readable read-only memory (DNA-ROM). While information can be 'written' error-free to a DNA-ROM array using appropriate sequence encodings its read accuracy can be affected by several factors such as array size, interconnect resistance, and Fermi energy deviations from HOMO levels of DNA strands employed in the crossbar. We study the impact of array size and interconnect resistance on the bit error rate of a DNA-ROM array through extensive Monte Carlo simulations. We have also analyzed the performance of our proposed DNA crossbar array for an image storage application, as a function of array size and interconnect resistance. While we expect that future advances in bioengineering and materials science will address some of the fabrication challenges associated with DNA crossbar arrays, we believe that the comprehensive body of results we present in this paper establishes the technical viability of DNA crossbar arrays as low power, high-density storage devices. Finally, our analysis of array performance vis-à-vis interconnect resistance should provide valuable insights into aspects of the fabrication process such as proper choice of interconnects necessary for ensuring high read accuracies.

Unity Human Eye Model for Gaze Tracking with a Query-Driven Dynamic Vision Sensor.

Objective measurement of gaze pattern and eye movement during untethered activity has important applications for neuroscience research and neurological disease detection. Current commercial eye-tracking tools rely on desk-top devices with infrared emitters and conventional frame-based cameras. Although wearable options do exist, the large power-consumption from their conventional cameras limit true long-term mobile usage. The query-driven Dynamic Vision Sensor (qDVS) is a neuromorphic camera which dramatically reduces power consumption by outputting only intensity-change threshold events, as opposed to full frames of intensity data. However, such hardware has not yet been implemented for on-body eye-tracking, but the feasibility can be demonstrated using a mathematical simulator to evaluate the eye-tracking ca-pabilities of the qDVS under controlled conditions. Specifically, a framework utilizing a realistic human eye model in the 3D graphics engine, Unity, is presented to enable the controlled and direct comparison of image-based gaze tracking methods. Eye-tracking based on qDVS frames was compared against two different conventional frame eye-tracking methods - the traditional ellipse pupil-fitting algorithm and a deep learning neural network inference model. Gaze accuracy from qDVS frames achieved an average of 93.2% for movement along the primary horizontal axis (pitch angle) and 93.1 % for movement along the primary vertical axis (yaw angle) under 4 different illumination conditions, demonstrating the feasibility for using qDVS hardware cameras for such applications. The quantitative framework for the direct comparison of eye tracking algorithms presented here is made open-source and can be extended to include other eye parameters, such as pupil dilation, reflection, motion artifact, and more.

A compute-in-memory chip based on resistive random-access memory.

Realizing increasingly complex artificial intelligence (AI) functionalities directly on edge devices calls for unprecedented energy efficiency of edge hardware. Compute-in-memory (CIM) based on resistive random-access memory (RRAM)1 promises to meet such demand by storing AI model weights in dense, analogue and non-volatile RRAM devices, and by performing AI computation directly within RRAM, thus eliminating power-hungry data movement between separate compute and memory2-5. Although recent studies have demonstrated in-memory matrix-vector multiplication on fully integrated RRAM-CIM hardware6-17, it remains a goal for a RRAM-CIM chip to simultaneously deliver high energy efficiency, versatility to support diverse models and software-comparable accuracy. Although efficiency, versatility and accuracy are all indispensable for broad adoption of the technology, the inter-related trade-offs among them cannot be addressed by isolated improvements on any single abstraction level of the design. Here, by co-optimizing across all hierarchies of the design from algorithms and architecture to circuits and devices, we present NeuRRAM-a RRAM-based CIM chip that simultaneously delivers versatility in reconfiguring CIM cores for diverse model architectures, energy efficiency that is two-times better than previous state-of-the-art RRAM-CIM chips across various computational bit-precisions, and inference accuracy comparable to software models quantized to four-bit weights across various AI tasks, including accuracy of 99.0 percent on MNIST18 and 85.7 percent on CIFAR-1019 image classification, 84.7-percent accuracy on Google speech command recognition20, and a 70-percent reduction in image-reconstruction error on a Bayesian image-recovery task.

A 3 mm × 3 mm Fully Integrated Wireless Power Receiver and Neural Interface System-on-Chip.

A miniaturized, fully integrated wireless power receiver system-on-chip with embedded 16-channel electrode array and data transceiver for electrocortical neural recording and stimulation is presented. An H-tree power and signal distribution network throughout the SoC maintains high quality factor up to 11 in the on-chip receiver coil at 144 MHz resonant frequency while rejecting RF interference in sensitive neural interface circuits owing to its perpendicular and equidistant geometry. A multi-mode buck-boost resonant regulating rectifier (B 2R 3) offers greater than 11-dB input dynamic range in RF reception and less than 1 mV overshoot in transient load regulation. At 10 mm link distance, the 9 mm 2 neural interface SoC fabricated in a 180 nm silicon-on-insulator (SOI) process attains an overall wireless power transmission system efficiency (WSE) of 3.4% in driving a 160  µW load yielding a WSE figure-of-merit of 131, while maintaining signal integrity in analog recording and wireless data transmission that comprise the on-chip load.

Error correction algorithm for high accuracy bio-impedance measurement in wearable healthcare applications.

Implantable and ambulatory measurement of physiological signals such as Bio-impedance using miniature biomedical devices needs careful tradeoff between limited power budget, measurement accuracy and complexity of implementation. This paper addresses this tradeoff through an extensive analysis of different stimulation and demodulation techniques for accurate Bio-impedance measurement. Three cases are considered for rigorous analysis of a generic impedance model, with multiple poles, which is stimulated using a square/sinusoidal current and demodulated using square/sinusoidal clock. For each case, the error in determining pole parameters (resistance and capacitance) is derived and compared. An error correction algorithm is proposed for square wave demodulation which reduces the peak estimation error from 9.3% to 1.3% for a simple tissue model. Simulation results in Matlab using ideal RC values show an average accuracy of for single pole and for two pole RC networks. Measurements using ideal components for a single pole model gives an overall and readings from saline phantom solution (primarily resistive) gives an . A Figure of Merit is derived based on ability to accurately resolve multiple poles in unknown impedance with minimal measurement points per decade, for given frequency range and supply current budget. This analysis is used to arrive at an optimal tradeoff between accuracy and power. Results indicate that the algorithm is generic and can be used for any application that involves resolving poles of an unknown impedance. It can be implemented as a post-processing technique for error correction or even incorporated into wearable signal monitoring ICs.

A generic miniature multi-feature programmable wireless powering headstage ASIC for implantable biomedical systems.

Wireless powering holds immense promise to enable a variety of implantable biomedical measurement systems with different power supply and current budget requirements. Effective power management demands more functionality in the headstage design like power level detection for range estimation and power save modes for sleep-wake operation. This paper proposes a single chip ASIC solution that addresses these problems by incorporating digitally programmable features and thus has the potential to enable wireless powering for many implantable systems. The ASIC includes an RF rectifier which has a peak efficiency of 17.9% at 900 MHz and 11.0% at 2.4 GHz, a robust 1 V bandgap reference and LDO voltage regulator whose output can be programmed in the range of 1 V-1.5 V, and can drive upto 4 mA of load current. The input RF power level detector has a threshold of 1.6 V and the power management block can be programmed to give a 6%, 12.5% or 25% duty cycle power line to the transmitter resulting in upto 60% reduction in average power. The ASIC was fabricated using the TSMC 65 nm process, occupies 1mm(2) die area and the headstage consumes ~300 µA at 1.2V regulated supply.