Tuning Hole-Injection in Organic-Light Emitting Diodes with Self-Assembled Monolayers.

Improving hole injection through the surface modification of indium tin oxide (ITO) with self-assembled monolayers (SAMs) is a promising method for modulating the carrier injection in organic light-emitting diodes (OLEDs). However, developing SAMs with the required characteristics remains a daunting challenge. Herein, we functionalize ITO with various phosphonic acid SAMs and evaluate the SAM-modified anodes in terms of their work function (WF), molecular distribution, coverage, and electrical conductivity. We fabricate and characterize green phosphorescent SAM-based OLEDs and compared their performance against devices based on the conventional poly(3,4-ethylenedioxythiophene):polystyrenesulfonate (PEDOT:PSS) hole-injection layer. We find that the usage of [2-(3,6-diiodo-9H-carbazol-9-yl)ethyl]phosphonic acid (I-2PACz) SAM yields devices with superior performance characteristics, including a maximum luminance of ∼57,300 cd m-2 and external quantum efficiency of up to ∼17%. This improvement is attributed to synergistic factors, including the deep WF of ITO/I-2PACz (5.47 eV), the formation of larger I-2PACz molecular clusters, and the intrinsic I-2PACz dipole, that collectively enhance hole-injection.

7D High-Dynamic Spin-Multiplexing.

Multiplexing technology creates several orthogonal data channels and dimensions for high-density information encoding and is irreplaceable in large-capacity information storage, and communication, etc. The multiplexing dimensions are constructed by light attributes and spatial dimensions. However, limited by the degree of freedom of interaction between light and material structure parameters, the multiplexing dimension exploitation method is still confused. Herein, a 7D Spin-multiplexing technique is proposed. Spin structures with four independent attributes (color center type, spin axis, spatial distribution, and dipole direction) are constructed as coding basic units. Based on the four independent spin physical effects, the corresponding photoluminescence wavelength, magnetic field, microwave, and polarization are created into four orthogonal multiplexing dimensions. Combined with the 3D of space, a 7D multiplexing method is established, which possesses the highest dimension number compared with 6 dimensions in the previous study. The basic spin unit is prepared by a self-developed laser-induced manufacturing process. The free state information of spin is read out by four physical quantities. Based on the multiple dimensions, the information is highly dynamically multiplexed to enhance information storage efficiency. Moreover, the high-dynamic in situ image encryption/marking is demonstrated. It implies a new paradigm for ultra-high-capacity storage and real-time encryption.

On the quality of commercial chemical vapour deposited hexagonal boron nitride.

The semiconductors industry has put its eyes on two-dimensional (2D) materials produced by chemical vapour deposition (CVD) because they can be grown at the wafer level with small thickness fluctuations, which is necessary to build electronic devices and circuits. However, CVD-grown 2D materials can contain significant amounts of lattice distortions, which degrades the performance at the device level and increases device-to-device variability. Here we statistically analyse the quality of commercially available CVD-grown hexagonal boron nitride (h-BN) from the most popular suppliers. h-BN is of strategic importance because it is one of the few insulating 2D materials, and can be used as anti-scattering substrate and gate dielectric. We find that the leakage current and electrical homogeneity of all commercially available CVD h-BN samples are significantly worse than those of mechanically exfoliated h-BN of similar thickness. Moreover, in most cases the properties of the CVD h-BN samples analysed don't match the technical specifications given by the suppliers, and the sample-to-sample variability is unsuitable for the reproducible fabrication of capacitors, transistors or memristors in different batches. In the short term, suppliers should try to provide accurate sample specifications matching the properties of the commercialized materials, and researchers should keep such inaccuracies in mind; and in the middle term suppliers should try to reduce the density of defects to enable the fabrication of high-performance devices with high reliability and reproducibility.

Programmable Optoelectronic Synaptic Transistors Based on MoS2/Ta2NiS5 Heterojunction for Energy-Efficient Neuromorphic Optical Operation.

The optoelectronic synaptic transistors with various functions, broad spectral perception, and low power consumption are an urgent need for the development of advanced optical neural network systems. However, it remains a great challenge to realize the functional diversification of the systems on a single device. 2D van der Waals (vdW) materials can combine unique properties by stacking with each other to form heterojunctions, which may provide a strategy for solving this problem. Herein, an all-2D vdW heterojunction-based programmable optoelectronic synaptic transistor based on MoS2/Ta2NiS5 heterojunctions is demonstrated. The device implements reconfigurable, multilevel non-volatile memory (NVM) states through sequential modulation of multiple optical and electrical stimuli to achieve broadband (532-808 nm), energy-efficient (17.2 fJ), hetero-synaptic functionality in a bionic manner. The intrinsic working mechanisms of the photogating effect caused by band alignment and the interfacial trapping defect modulation induced by gate voltage are revealed by Kelvin-probe force microscopy (KPFM) measurements and carrier transport analysis. Overall, the (opto)electronic synaptic weight controllability for combined in-sensor and in-memory logic processors is realized by the heterojunction properties. The proposed findings facilitate the technical realization of generic all 2D hetero-synapses for future artificial vision systems, opto-logical systems, and Internet of Things (IoT) entities.

Hardware implementation of memristor-based artificial neural networks.

Artificial Intelligence (AI) is currently experiencing a bloom driven by deep learning (DL) techniques, which rely on networks of connected simple computing units operating in parallel. The low communication bandwidth between memory and processing units in conventional von Neumann machines does not support the requirements of emerging applications that rely extensively on large sets of data. More recent computing paradigms, such as high parallelization and near-memory computing, help alleviate the data communication bottleneck to some extent, but paradigm- shifting concepts are required. Memristors, a novel beyond-complementary metal-oxide-semiconductor (CMOS) technology, are a promising choice for memory devices due to their unique intrinsic device-level properties, enabling both storing and computing with a small, massively-parallel footprint at low power. Theoretically, this directly translates to a major boost in energy efficiency and computational throughput, but various practical challenges remain. In this work we review the latest efforts for achieving hardware-based memristive artificial neural networks (ANNs), describing with detail the working principia of each block and the different design alternatives with their own advantages and disadvantages, as well as the tools required for accurate estimation of performance metrics. Ultimately, we aim to provide a comprehensive protocol of the materials and methods involved in memristive neural networks to those aiming to start working in this field and the experts looking for a holistic approach.

Thermal Compact Modeling and Resistive Switching Analysis in Titanium Oxide-Based Memristors.

Resistive switching devices based on the Au/Ti/TiO2/Au stack were developed. In addition to standard electrical characterization by means of I-V curves, scanning thermal microscopy was employed to localize the hot spots on the top device surface (linked to conductive nanofilaments, CNFs) and perform in-operando tracking of temperature in such spots. In this way, electrical and thermal responses can be simultaneously recorded and related to each other. In a complementary way, a model for device simulation (based on COMSOL Multiphysics) was implemented in order to link the measured temperature to simulated device temperature maps. The data obtained were employed to calculate the thermal resistance to be used in compact models, such as the Stanford model, for circuit simulation. The thermal resistance extraction technique presented in this work is based on electrical and thermal measurements instead of being indirectly supported by a single fitting of the electrical response (using just I-V curves), as usual. Besides, the set and reset voltages were calculated from the complete I-V curve resistive switching series through different automatic numerical methods to assess the device variability. The series resistance was also obtained from experimental measurements, whose value is also incorporated into a compact model enhanced version.

Anisotropic Superconducting Nb2 CTx MXene Processed by Atomic Exchange at the Wafer Scale.

Superconductivty has recently been induced in MXenes through surface modification. However, the previous reports have mostly been based on powders or cold-pressed pellets, with no known reports on the intrinsic superconsucting properties of MXenes at the nanoale. Here, it is developed a high-temperature atomic exchange process in NH3 atmosphere which induces superconductivity in either singleflakes or thin films of Nb2 CTx MXene. The exchange process between nitrogen atoms and fluorine, carbon, and oxygen atoms in the MXene lattice and related structural adjustments are studied using both experiments and density functional theory. Using either single-flake or thin-film devices, an anisotropic magnetic response of the 2D superconducting transformation has been successfully revealed. The anisotropic superconductivity is further demonstrated using superconducting thin films uniformly deposited over a 4 in. wafers, which opens up the possibility of scalable MXene-based superconducting devices.

Nonepitaxial Wafer-Scale Single-Crystal 2D Materials on Insulators.

Next-generation nanodevices require 2D material synthesis on insulating substrates. However, growing high-quality 2D-layered materials, such as hexagonal boron nitride (hBN) and graphene, on insulators is challenging owing to the lack of suitable metal catalysts, imperfect lattice matching with substrates, and other factors. Therefore, developing a generally applicable approach for realizing high-quality 2D layers on insulators remains crucial, despite numerous strategies being explored. Herein, a universal strategy is introduced for the nonepitaxial synthesis of wafer-scale single-crystal 2D materials on arbitrary insulating substrates. The metal foil in a nonadhered metal-insulator substrate system is almost melted by a brief high-temperature treatment, thereby pressing the as-grown 2D layers to well attach onto the insulators. High-quality, large-area, single-crystal, monolayer hBN and graphene films are synthesized on various insulating substrates. This strategy provides new pathways for synthesizing various 2D materials on arbitrary insulators and offers a universal epitaxial platform for future single-crystal film production.

High-performance van der Waals antiferroelectric CuCrP2S6-based memristors.

Layered thio- and seleno-phosphate ferroelectrics, such as CuInP2S6, are promising building blocks for next-generation nonvolatile memory devices. However, because of the low Curie point, the CuInP2S6-based memory devices suffer from poor thermal stability (<42 °C). Here, exploiting the electric field-driven phase transition in the rarely studied antiferroelectric CuCrP2S6 crystals, we develop a nonvolatile memristor showing a sizable resistive-switching ratio of ~ 1000, high switching endurance up to 20,000 cycles, low cycle-to-cycle variation, and robust thermal stability up to 120 °C. The resistive switching is attributed to the ferroelectric polarization-modulated thermal emission accompanied by the Fowler-Nordheim tunneling across the interfaces. First-principles calculations reveal that the good device performances are associated with the exceptionally strong ferroelectric polarization in CuCrP2S6 crystal. Furthermore, the typical biological synaptic learning rules, such as long-term potentiation/depression and spike amplitude/spike time-dependent plasticity, are also demonstrated. The results highlight the great application potential of van der Waals antiferroelectrics in high-performance synaptic devices for neuromorphic computing.

Current-Limited Conductive Atomic Force Microscopy.

Conductive atomic force microscopy (CAFM) has become the preferred tool of many companies and academics to analyze the electronic properties of materials and devices at the nanoscale. This technique scans the surface of a sample using an ultrasharp conductive nanoprobe so that the contact area between them is very small (<100 nm2) and it can measure the properties of the sample with a very high lateral resolution. However, measuring relatively low currents (∼1 nA) in such small areas produces high current densities (∼1000 A/cm2), which almost always results in fast nanoprobe degradation. That is not only expensive but also endangers the reliability of the data collected because detecting which data sets are affected by tip degradation can be complex. Here, we show an inexpensive long-sought solution for this problem by using a current limitation system. We test its performance by measuring the tunneling current across a reference ultrathin dielectric when applying ramped voltage stresses at hundreds of randomly selected locations of its surface, and we conclude that the use of a current limitation system increases the lifetime of the tips by a factor of ∼50. Our work contributes to significantly enhance the reliability of one of the most important characterization techniques in the field of nanoelectronics.

Spatially-Resolved Thermometry of Filamentary Nanoscale Hot Spots in TiO2 Resistive Random Access Memories to Address Device Variability.

Resistive random access memories (RRAM), based on the formation and rupture of conductive nanoscale filaments, have attracted increased attention for application in neuromorphic and in-memory computing. However, this technology is, in part, limited by its variability, which originates from the stochastic formation and extreme heating of its nanoscale filaments. In this study, we used scanning thermal microscopy (SThM) to assess the effect of filament-induced heat spreading on the surface of metal oxide RRAMs with different device designs. We evaluate the variability of TiO2 RRAM devices with area sizes of 2 × 2 and 5 × 5 µm2. Electrical characterization shows that the variability indicated by the standard deviation of the forming voltage is ∼2 times larger for 5 × 5 µm2 devices than for the 2 × 2 µm2 ones. Further knowledge on the reason for this variability is gained through the SThM thermal maps. These maps show that for 2 × 2 µm2 devices the formation of one filament, i.e., hot spot at the device surface, happens reliably at the same location, while the filament location varies for the 5 × 5 µm2 devices. The thermal information, combined with the electrical, interfacial, and geometric characteristics of the device, provides additional insights into the operation and variability of RRAMs. This work suggests thermal engineering and characterization routes to optimize the efficiency and reliability of these devices.

Recent Advances and Future Prospects for Memristive Materials, Devices, and Systems.

Memristive technology has been rapidly emerging as a potential alternative to traditional CMOS technology, which is facing fundamental limitations in its development. Since oxide-based resistive switches were demonstrated as memristors in 2008, memristive devices have garnered significant attention due to their biomimetic memory properties, which promise to significantly improve power consumption in computing applications. Here, we provide a comprehensive overview of recent advances in memristive technology, including memristive devices, theory, algorithms, architectures, and systems. In addition, we discuss research directions for various applications of memristive technology including hardware accelerators for artificial intelligence, in-sensor computing, and probabilistic computing. Finally, we provide a forward-looking perspective on the future of memristive technology, outlining the challenges and opportunities for further research and innovation in this field. By providing an up-to-date overview of the state-of-the-art in memristive technology, this review aims to inform and inspire further research in this field.

Cellular automata imbedded memristor-based recirculated logic in-memory computing.

Memristor-based circuits offer low hardware costs and in-memory computing, but full-memristive circuit integration for different algorithm remains limited. Cellular automata (CA) has been noticed for its well-known parallel, bio-inspired, computational characteristics. Running CA on conventional chips suffers from low parallelism and high hardware costs. Establishing dedicated hardware for CA remains elusive. We propose a recirculated logic operation scheme (RLOS) using memristive hardware and 2D transistors for CA evolution, significantly reducing hardware complexity. RLOS's versatility supports multiple CA algorithms on a single circuit, including elementary CA rules and more complex majority classification and edge detection algorithms. Results demonstrate up to a 79-fold reduction in hardware costs compared to FPGA-based approaches. RLOS-based reservoir computing is proposed for edge computing development, boasting the lowest hardware cost (6 components/per cell) among existing implementations. This work advances efficient, low-cost CA hardware and encourages edge computing hardware exploration.

Inkjet-printed h-BN memristors for hardware security.

Inkjet printing electronics is a growing market that reached 7.8 billion USD in 2020 and that is expected to grow to ∼23 billion USD by 2026, driven by applications like displays, photovoltaics, lighting, and radiofrequency identification. Incorporating two-dimensional (2D) materials into this technology could further enhance the properties of the existing devices and/or circuits, as well as enable the development of new concept applications. Along these lines, here we report an easy and cheap process to synthesize inks made of multilayer hexagonal boron nitride (h-BN)-an insulating 2D layered material-by the liquid-phase exfoliation method and use them to fabricate memristors. The devices exhibit multiple stochastic phenomena that are very attractive for use as entropy sources in electronic circuits for data encryption (physical unclonable functions [PUFs], true random number generators [TRNGs]), such as: (i) a very disperse initial resistance and dielectric breakdown voltage, (ii) volatile unipolar and non-volatile bipolar resistive switching (RS) with a high cycle-to-cycle variability of the state resistances, and (iii) random telegraph noise (RTN) current fluctuations. The clue for the observation of these stochastic phenomena resides on the unpredictable nature of the device structure derived from the inkjet printing process (i.e., thickness fluctuations, random flake orientations), which allows fabricating electronic devices with different electronic properties. The easy-to-make and cheap memristors here developed are ideal to encrypt the information produced by multiple types of objects and/or products, and the versatility of the inkjet printing method, which allows effortless deposition on any substrate, makes our devices especially attractive for flexible and wearable devices within the internet-of-things.

Nanoscale temperature sensing of electronic devices with calibrated scanning thermal microscopy.

Heat dissipation threatens the performance and lifetime of many electronic devices. As the size of devices shrinks to the nanoscale, we require spatially and thermally resolved thermometry to observe their fine thermal features. Scanning thermal microscopy (SThM) has proven to be a versatile measurement tool for characterizing the temperature at the surface of devices with nanoscale resolution. SThM can obtain qualitative thermal maps of a device using an operating principle based on a heat exchange process between a thermo-sensitive probe and the sample surface. However, the quantification of these thermal features is one of the most challenging parts of this technique. Developing reliable calibration approaches for SThM is therefore an essential aspect to accurately determine the temperature at the surface of a sample or device. In this work, we calibrate a thermo-resistive SThM probe using heater-thermometer metal lines with different widths (50 nm to 750 nm), which mimic variable probe-sample thermal exchange processes. The sensitivity of the SThM probe when scanning the metal lines is also evaluated under different probe and line temperatures. Our results reveal that the calibration factor depends on the probe measuring conditions and on the size of the surface heating features. This approach is validated by mapping the temperature profile of a phase change electronic device. Our analysis provides new insights on how to convert the thermo-resistive SThM probe signal to the scanned device temperature more accurately.

Holistic Variability Analysis in Resistive Switching Memories Using a Two-Dimensional Variability Coefficient.

We present a new methodology to quantify the variability of resistive switching memories. Instead of statistically analyzing few data points extracted from current versus voltage (I-V) plots, such as switching voltages or state resistances, we take into account the whole I-V curve measured in each RS cycle. This means going from a one-dimensional data set to a two-dimensional data set, in which every point of each I-V curve measured is included in the variability calculation. We introduce a new coefficient (named two-dimensional variability coefficient, 2DVC) that reveals additional variability information to which traditional one-dimensional analytical methods (such as the coefficient of variation) are blind. This novel approach provides a holistic variability metric for a better understanding of the functioning of resistive switching memories.

Solid Platinum Nanoprobes for Highly Reliable Conductive Atomic Force Microscopy.

Conductive atomic force microscopy (CAFM) is a powerful technique to investigate electrical and mechanical properties of materials and devices at the nanoscale. However, its main challenge is the reliability of the probe tips and their interaction with the samples. The most common probe tips used in CAFM studies are made of Si coated with a thin (∼20 nm) film of Pt or Pt-rich alloys (such as Pt/Ir), but this can degrade fast due to high current densities (>102A/cm2) and mechanical frictions. Si tips coated with doped diamond and solid doped diamond tips are more durable, but they are significantly more expensive and their high stiffness often damages the surface of most samples. One growing alternative is to use solid Pt tips, which have an intermediate price and are expected to be more durable than metal-coated silicon tips. However, a thorough characterization of the performance of solid Pt probes for CAFM research has never been reported. In this article, we characterize the performance of solid Pt probes for nanoelectronics research by performing various types of experiments and compare them to Pt/Ir-coated Si probes. Our results indicate that solid Pt probes exhibit a lateral resolution that is very similar to that of Pt/Ir-coated Si probes but with the big advantage of a much longer lifetime. Moreover, the probe-to-probe deviation of the electrical data collected is small. The use of solid Pt probes can help researchers to enhance the reliability of their CAFM experiments.

Hybrid 2D-CMOS microchips for memristive applications.

Exploiting the excellent electronic properties of two-dimensional (2D) materials to fabricate advanced electronic circuits is a major goal for the semiconductor industry1,2. However, most studies in this field have been limited to the fabrication and characterization of isolated large (more than 1 µm2) devices on unfunctional SiO2-Si substrates. Some studies have integrated monolayer graphene on silicon microchips as a large-area (more than 500 µm2) interconnection3 and as a channel of large transistors (roughly 16.5 µm2) (refs. 4,5), but in all cases the integration density was low, no computation was demonstrated and manipulating monolayer 2D materials was challenging because native pinholes and cracks during transfer increase variability and reduce yield. Here, we present the fabrication of high-integration-density 2D-CMOS hybrid microchips for memristive applications-CMOS stands for complementary metal-oxide-semiconductor. We transfer a sheet of multilayer hexagonal boron nitride onto the back-end-of-line interconnections of silicon microchips containing CMOS transistors of the 180 nm node, and finalize the circuits by patterning the top electrodes and interconnections. The CMOS transistors provide outstanding control over the currents across the hexagonal boron nitride memristors, which allows us to achieve endurances of roughly 5 million cycles in memristors as small as 0.053 µm2. We demonstrate in-memory computation by constructing logic gates, and measure spike-timing dependent plasticity signals that are suitable for the implementation of spiking neural networks. The high performance and the relatively-high technology readiness level achieved represent a notable advance towards the integration of 2D materials in microelectronic products and memristive applications.

Hardware implementation of a true random number generator integrating a hexagonal boron nitride memristor with a commercial microcontroller.

The development of the internet-of-things requires cheap, light, small and reliable true random number generator (TRNG) circuits to encrypt the data-generated by objects or humans-before transmitting them. However, all current solutions consume too much power and require a relatively large battery, hindering the integration of TRNG circuits on most objects. Here we fabricated a TRNG circuit by exploiting stable random telegraph noise (RTN) current signals produced by memristors made of two-dimensional (2D) multi-layered hexagonal boron nitride (h-BN) grown by chemical vapor deposition and coupled with inkjet-printed Ag electrodes. When biased at small constant voltages (≤70 mV), the Ag/h-BN/Ag memristors exhibit RTN signals with very low power consumption (∼5.25 nW) and a relatively high current on/off ratio (∼2) for long periods (>1 hour). We constructed TRNG circuits connecting an h-BN memristor to a small, light and cheap commercial microcontroller, producing a highly-stochastic, high-throughput signal (up to 7.8 Mbit s-1) even if the RTN at the input gets interrupted for long times up to 20 s, and if the stochasticity of the RTN signal is reduced. Our study presents the first full hardware implementation of 2D-material-based TRNGs, enabled by the unique stability and figures of merit of the RTN signals in h-BN based memristors.