Temperature and layer thickness dependent in situ investigations on epindolidione organic thin-film transistors.

We report on in situ performance evaluations as a function of layer thickness and substrate temperature for bottom-gate, bottom-gold contact epindolidione organic thin-film transistors on various gate dielectrics. Experiments were carried out under ultra-high vacuum conditions, enabling quasi-simultaneous electrical and surface analysis. Auger electron spectroscopy and thermal desorption spectroscopy (TDS) were applied to characterize the quality of the substrate surface and the thermal stability of the organic films. Ex situ atomic force microscopy (AFM) was used to gain additional information on the layer formation and surface morphology of the hydrogen-bonded organic pigment. The examined gate dielectrics included SiO2, in its untreated and sputtered forms, as well as the spin-coated organic capping layers poly(vinyl-cinnamate) (PVCi) and poly((±)endo,exo-bicyclo[2.2.1]hept-5-ene-2,3-dicarboxylic acid, diphenylester) (PNDPE, from the class of polynorbornenes). TDS and AFM revealed Volmer-Weber island growth dominated film formation with no evidence of a subjacent wetting layer. This growth mode is responsible for the comparably high coverage required for transistor behavior at 90-95% of a monolayer composed of standing molecules. Surface sputtering and an increased sample temperature during epindolidione deposition augmented the surface diffusion of adsorbing molecules and therefore led to a lower number of better-ordered islands. Consequently, while the onset of charge transport was delayed, higher saturation mobility was obtained. The highest, bottom-contact configuration, mobilities of approximately 2.5 × 10-3cm2/Vs were found for high coverages (50 nm) on sputtered samples. The coverage dependence of the mobility showed very different characteristics for the different gate dielectrics, while the change of the threshold voltage with coverage was approximately the same for all systems. An apparent decrease of the mobility with increasing coverage on the less polar PNDPE was attributed to a change in molecular orientation from upright standing in the thin-film phase to tilted in the bulk phase. From temperature-dependent mobility measurements we calculated activation barriers for the charge transport between 110 meV and 160 meV, depending on the dielectric configuration.

Optimizing pentacene thin-film transistor performance: Temperature and surface condition induced layer growth modification.

In this work we present in situ electrical and surface analytical, as well as ex situ atomic force microscopy (AFM) studies on temperature and surface condition induced pentacene layer growth modifications, leading to the selection of optimized deposition conditions and entailing performance improvements. We prepared p++-silicon/silicon dioxide bottom-gate, gold bottom-contact transistor samples and evaluated the pentacene layer growth for three different surface conditions (sputtered, sputtered + carbon and unsputtered + carbon) at sample temperatures during deposition of 200 K, 300 K and 350 K. The AFM investigations focused on the gold contacts, the silicon dioxide channel region and the highly critical transition area. Evaluations of coverage dependent saturation mobilities, threshold voltages and corresponding AFM analysis were able to confirm that the first 3-4 full monolayers contribute to the majority of charge transport within the channel region. At high temperatures and on sputtered surfaces uniform layer formation in the contact-channel transition area is limited by dewetting, leading to the formation of trenches and the partial development of double layer islands within the channel region instead of full wetting layers. By combining the advantages of an initial high temperature deposition (well-ordered islands in the channel) and a subsequent low temperature deposition (continuous film formation for low contact resistance) we were able to prepare very thin (8 ML) pentacene transistors of comparably high mobility.

In situ preparation, electrical and surface analytical characterization of pentacene thin film transistors.

The fabrication of organic thin film transistors with highly reproducible characteristics presents a very challenging task. We have prepared and analyzed model pentacene thin film transistors under ultra-high vacuum conditions, employing surface analytical tools and methods. Intentionally contaminating the gold contacts and SiO2 channel area with carbon through repeated adsorption, dissociation, and desorption of pentacene proved to be very advantageous in the creation of devices with stable and reproducible parameters. We mainly focused on the device properties, such as mobility and threshold voltage, as a function of film morphology and preparation temperature. At 300 K, pentacene displays Stranski-Krastanov growth, whereas at 200 K fine-grained, layer-like film growth takes place, which predominantly influences the threshold voltage. Temperature dependent mobility measurements demonstrate good agreement with the established multiple trapping and release model, which in turn indicates a predominant concentration of shallow traps in the crystal grains and at the oxide-semiconductor interface. Mobility and threshold voltage measurements as a function of coverage reveal that up to four full monolayers contribute to the overall charge transport. A significant influence on the effective mobility also stems from the access resistance at the gold contact-semiconductor interface, which is again strongly influenced by the temperature dependent, characteristic film growth mode.