Layer-resolved release of epitaxial layers in III-V heterostructure via a buffer-free mechanical separation technique.

Layer-release techniques for producing freestanding III-V epitaxial layers have been actively developed for heterointegration of single-crystalline compound semiconductors with Si platforms. However, for the release of target epitaxial layers from III-V heterostructures, it is required to embed a mechanically or chemically weak sacrificial buffer beneath the target layers. This requirement severely limits the scope of processable materials and their epi-structures and makes the growth and layer-release process complicated. Here, we report that epitaxial layers in commonly used III-V heterostructures can be precisely released with an atomic-scale surface flatness via a buffer-free separation technique. This result shows that heteroepitaxial interfaces of a normal lattice-matched III-V heterostructure can be mechanically separated without a sacrificial buffer and the target interface for separation can be selectively determined by adjusting process conditions. This technique of selective release of epitaxial layers in III-V heterostructures will provide high fabrication flexibility in compound semiconductor technology.

Simultaneous Extraction of the Grain Size, Single-Crystalline Grain Sheet Resistance, and Grain Boundary Resistivity of Polycrystalline Monolayer Graphene.

The electrical properties of polycrystalline graphene grown by chemical vapor deposition (CVD) are determined by grain-related parameters-average grain size, single-crystalline grain sheet resistance, and grain boundary (GB) resistivity. However, extracting these parameters still remains challenging because of the difficulty in observing graphene GBs and decoupling the grain sheet resistance and GB resistivity. In this work, we developed an electrical characterization method that can extract the average grain size, single-crystalline grain sheet resistance, and GB resistivity simultaneously. We observed that the material property, graphene sheet resistance, could depend on the device dimension and developed an analytical resistance model based on the cumulative distribution function of the gamma distribution, explaining the effect of the GB density and distribution in the graphene channel. We applied this model to CVD-grown monolayer graphene by characterizing transmission-line model patterns and simultaneously extracted the average grain size (~5.95 µm), single-crystalline grain sheet resistance (~321 Ω/sq), and GB resistivity (~18.16 kΩ-µm) of the CVD-graphene layer. The extracted values agreed well with those obtained from scanning electron microscopy images of ultraviolet/ozone-treated GBs and the electrical characterization of graphene devices with sub-micrometer channel lengths.