A Novel Source/Drain Extension Scheme with Laser-Spike Annealing for Nanosheet Field-Effect Transistors in 3D ICs.

This study proposed a novel source/drain (S/D) extension scheme to increase the stress in nanosheet (NS) field-effect transistors (NSFETs) and investigated the scheme by using technology-computer-aided-design simulations. In three-dimensional integrated circuits, transistors in the bottom tier were exposed to subsequent processes; therefore, selective annealing, such as laser-spike annealing (LSA), should be applied. However, the application of the LSA process to NSFETs significantly decreased the on-state current (Ion) owing to diffusionless S/D dopants. Furthermore, the barrier height below the inner spacer was not lowered even under on-state bias conditions because ultra-shallow junctions between the NS and S/D were formed far from the gate metal. However, the proposed S/D extension scheme overcame these Ion reduction issues by adding an NS-channel-etching process before S/D formation. A larger S/D volume induced a larger stress in the NS channels; thus, the stress was boosted by over 25%. Additionally, an increase in carrier concentrations in the NS channels improved Ion. Therefore, Ion increased by approximately 21.7% (37.4%) in NFETs (PFETs) compared with NSFETs without the proposed scheme. Additionally, the RC delay was improved by 2.03% (9.27%) in NFETs (PFETs) compared with NSFETs using rapid thermal annealing. Therefore, the S/D extension scheme overcame the Ion reduction issues encountered in LSA and significantly enhanced the AC/DC performance.

Sensitivity of Inner Spacer Thickness Variations for Sub-3-nm Node Silicon Nanosheet Field-Effect Transistors.

The inner spacer thickness (TIS) variations in sub-3-nm, node 3-stacked, nanosheet field-effect transistors (NSFETs) were investigated using computer-aided design simulation technology. Inner spacer formation requires a high selectivity of SiGe to Si, which causes inevitable TIS variation (ΔTIS). The gate length (LG) depends on the TIS. Thus, the DC/AC performance is significantly affected by ΔTIS. Because the effects of ΔTIS on the performance depend on which inner spacer is varied, the sensitivities of the performance to the top, middle, and bottom (T, M, and B, respectively) ΔTIS should be studied separately. In addition, the source/drain (S/D) recess process variation that forms the parasitic bottom transistor (trpbt) should be considered with ΔTIS because the gate controllability over trpbt is significantly dependent on ΔTIS,B. If the S/D recess depth (TSD) variation cannot be completely eliminated, reducing ΔTIS,B is crucial for suppressing the effects of trpbt. It is noteworthy that reducing ΔTIS,B is the most important factor when the TSD variation occurs, whereas reducing ΔTIS,T and ΔTIS,M is crucial in the absence of TSD variation to minimize the DC performance variation. As the TIS increases, the gate capacitance (Cgg) decreases owing to the reduction in both parasitic and intrinsic capacitance, but the sensitivity of Cgg to each ΔTIS is almost the same. Therefore, the difference in performance sensitivity related to AC response is also strongly affected by the DC characteristics. In particular, since TSD of 5 nm increases the off-state current (Ioff) sensitivity to ΔTIS,B by a factor of 22.5 in NFETs, the ΔTIS,B below 1 nm is essential for further scaling and yield enhancement.

Novel Modeling Approach to Analyze Threshold Voltage Variability in Short Gate-Length (15-22 nm) Nanowire FETs with Various Channel Diameters.

In this study, threshold voltage (Vth) variability was investigated in silicon nanowire field-effect transistors (SNWFETs) with short gate-lengths of 15-22 nm and various channel diameters (DNW) of 7, 9, and 12 nm. Linear slope and nonzero y-intercept were observed in a Pelgrom plot of the standard deviation of Vth (σVth), which originated from random and process variations. Interestingly, the slope and y-intercept differed for each DNW, and σVth was the smallest at a median DNW of 9 nm. To analyze the observed DNW tendency of σVth, a novel modeling approach based on the error propagation law was proposed. The contribution of gate-metal work function, channel dopant concentration (Nch), and DNW variations (WFV, ∆Nch, and ∆DNW) to σVth were evaluated by directly fitting the developed model to measured σVth. As a result, WFV induced by metal gate granularity increased as channel area increases, and the slope of WFV in Pelgrom plot is similar to that of σVth. As DNW decreased, SNWFETs became robust to ∆Nch but vulnerable to ∆DNW. Consequently, the contribution of ∆DNW, WFV, and ∆Nch is dominant at DNW of 7 nm, 9 nm, and 12, respectively. The proposed model enables the quantifying of the contribution of various variation sources of Vth variation, and it is applicable to all SNWFETs with various LG and DNW.