A 2.4 GHz ULP reconfigurable asymmetric transceiver for single-chip wireless neural recording IC.

This paper presents a 2.4 GHz ultra-low-power (ULP) reconfigurable asymmetric transceiver and demonstrates its application in wireless neural recording. Fabricated in 0.13 µm CMOS technology, the transceiver is optimized for sensor-gateway communications within a star-shaped network, and supports both the sensor and gateway operation modes. Binary phase-shift keying (BPSK) modulation with high data rate (DR) of 1 to 8 Mbps is used in the uplink from sensor to gateway, while on-off keying (OOK) modulation with low DR of 100 kbps is adopted in the downlink. A fully integrated Class-E PA with moderate output power has also been proposed and achieves power efficiency of 53%. To minimize area usage, inductor reuse is adopted between PA and LNA, and eliminates the need of lossy T/R switch in the RF signal path. When used as sensor, the transceiver with frequency locked phase-locked loop (PLL) achieves TX (BPSK) power efficiency of 28% @ 0 dBm output power, and RX (OOK) sensitivity of -80 dBm @ 100 kbps while consuming only 780 µW . When configured as gateway, the transceiver achieves sensitivity levels of -92, -84.5, and -77 dBm for 1, 5, and 8 Mbps BPSK, respectively. The transceiver is integrated with an 8-channel neural recording front-end, and neural signals from a rat are captured to verify the system functionality.

A 0.7-V 17.4- µ W 3-lead wireless ECG SoC.

This paper presents a fully integrated sub-1 V 3-lead wireless ECG System-on-Chip (SoC) for wireless body sensor network applications. The SoC includes a two-channel ECG front-end with a driven-right-leg circuit, an 8-bit SAR ADC, a custom-designed 16-bit microcontroller, two banks of 16 kb SRAM, and a MICS band transceiver. The microcontroller and SRAM blocks are able to operate at sub-/near-threshold regime for the best energy consumption. The proposed SoC has been implemented in a standard 0.13- µ m CMOS process. Measurement results show the microcontroller consumes only 2.62 pJ per instruction at 0.35 V . Both microcontroller and memory blocks are functional down to 0.25 V. The entire SoC is capable of working at single 0.7-V supply. At the best case, it consumes 17.4 µ W in heart rate detection mode and 74.8 µW in raw data acquisition mode under sampling rate of 500 Hz. This makes it one of the best ECG SoCs among state-of-the-art biomedical chips.