In Situ Growth of Wafer-Scale Patterned Graphene and Fabrication of Optoelectronic Artificial Synaptic Device Array Based on Graphene/n-AlGaN Heterojunction for Visual Learning.

The unique optical and electrical properties of graphene-based heterojunctions make them significant for artificial synaptic devices, promoting the advancement of biomimetic vision systems. However, mass production and integration of device arrays are necessary for visual imaging, which is still challenging due to the difficulty in direct growth of wafer-scale graphene patterns. Here, a novel strategy is proposed using photosensitive polymer as a solid carbon source for in situ growth of patterned graphene on diverse substrates. The growth mechanism during high-temperature annealing is elucidated, leading to wafer-scale graphene patterns with exceptional uniformity, ideal crystalline quality, and precise control over layer number by eliminating the release of volatile from oxygen-containing resin. The growth strategy enables the fabrication of two-inch optoelectronic artificial synaptic device array based on graphene/n-AlGaN heterojunction, which emulates key functionalities of biological synapses, including short-term plasticity, long-term plasticity, and spike-rate-dependent plasticity. Moreover, the mimicry of visual learning in the human brain is attributed to the regulation of excitatory and inhibitory post-synapse currents, following a learning rule that prioritizes initial recognition before memory formation. The duration of long-term memory reaches 10 min. The in situ growth strategy for patterned graphene represents the novelty for fabricating fundamental hardware of an artificial neuromorphic system.

Plasmonic-enhanced efficiency of AlGaN-based deep ultraviolet LED by graphene/Al nanoparticles/graphene hybrid structure.

The AlGaN-based deep ultraviolet light-emitting diode (DUV LED) has advantages of environmentally friendly materials, tunable emission wavelength, and easy miniaturization. However, the light extraction efficiency (LEE) of an AlGaN-based DUV LED is low, which hinders its applications. Here, we design a graphene/Al nanoparticles/graphene (Gra/Al NPs/Gra) hybrid plasmonic structure, where the strong resonant coupling of local surface plasmons (LSPs) induces a 2.9-times enhancement for the LEE of the DUV LED according to the photoluminescence (PL). The dewetting of Al NPs on a graphene layer by annealing is optimized, resulting in better formation and uniform distribution. The near-field coupling of Gra/Al NPs/Gra is enhanced via charge transfer among graphene and Al NPs. In addition, the skin depth increment results in more excitons being coupled out of multiple quantum wells (MQWs). An enhanced mechanism is proposed, revealing that the Gra/metal NPs/Gra offers a reliable strategy for improving the optoelectronic device performance, which might trigger the advances of LEDs and lasers with high brightness and power density.

Strain-Reduced Micro-LEDs Grown Directly Using Partitioned Growth.

Strain-reduced micro-LEDs in 50 µm × 50 µm, 100 µm × 100 µm, 200 µm × 200 µm, 500 µm × 500 µm, and 1,000 µm × 1,000 µm sizes were grown on a patterned c-plane sapphire substrate using partitioned growth with the metal-organic chemical-vapor deposition (MOCVD) technique. The size effect on the optical properties and the indium concentration for the quantum wells were studied experimentally. Here, we revealed that the optical properties can be improved by decreasing the chip size (from 1,000 to 100 µm), which can correspondingly reduce the in-plane compressive stress. However, when the chip size is further reduced to 50 µm × 50 µm, the benefit of strain release is overridden by additional defects induced by the higher indium incorporation in the quantum wells and the efficiency of the device decreases. The underlying mechanisms of the changing output power are uncovered based on different methods of characterization. This work shows the rules of thumb to achieve optimal power performance for strain-reduced micro-LEDs through the proposed partitioned growth process.

Experimental and Modeling Investigations of Miniaturization in InGaN/GaN Light-Emitting Diodes and Performance Enhancement by Micro-Wall Architecture.

The recent technological trends toward miniaturization in lighting and display devices are accelerating the requirement for high-performance and small-scale GaN-based light-emitting diodes (LEDs). In this work, the effect of mesa size-reduction in the InGaN/GaN LEDs is systematically investigated in two lateral dimensions (x- and y-directions: parallel to and perpendicular to the line where p-n directions are) both experimentally and numerically. The role of the lateral size-reduction in the x- and y-directions in improving LED performance is separately identified through experimental and modeling investigations. The narrowed dimension in the x-direction is found to cause and dominate the alleviated current crowding phenomenon, while the size-reduction in the y-direction has a minor influence on that. The size-reduction in the y-orientation induces an increased ratio of perimeter-to-area in miniaturized LED devices, which leads to improved thermal dissipation and light extraction through the sidewalls. The grown and fabricated LED devices with varied dimensions further support this explanation. Then the effect of size-reduction on the LED performance is summarized. Moreover, three-micro-walls LED architecture is proposed and demonstrated to further promote light extraction and reduce the generation of the Joule heat. The findings in this work provide instructive guidelines and insights on device miniaturization, especially for micro-LED devices.

On the mechanisms of InGaN electron cooler in InGaN/GaN light-emitting diodes.

Electron overflow limits the quantum efficiency of InGaN/GaN light-emitting diodes. InGaN electron cooler (EC) can be inserted before growing InGaN/GaN multiple quantum wells (MQWs) to reduce electron overflow. However, detailed mechanisms of how the InGaN EC contributes to the efficiency improvement have remained unclear so far. In this work, we theoretically propose and experimentally demonstrate an electron mean-free-path model, which reveals the InGaN EC reduces the electron mean free path in MQWs, increases the electron capture rate and also reduces the valence band barrier heights of the MQWs, in turn promoting the hole transport into MQWs.

On the effect of N-GaN/P-GaN/N-GaN/P-GaN/N-GaN built-in junctions in the n-GaN layer for InGaN/GaN light-emitting diodes.

N-GaN/P-GaN/N-GaN/P-GaN/N-GaN (NPNPN-GaN) junctions embedded between the n-GaN region and multiple quantum wells (MQWs) are systematically studied both experimentally and theoretically to increase the performance of InGaN/GaN light emitting diodes (LEDs) in this work. In the proposed architecture, each thin P-GaN layer sandwiched in the NPNPN-GaN structure is completely depleted due to the built-in electric field in the NPNPN-GaN junctions, and the ionized acceptors in these P-GaN layers serve as the energy barriers for electrons from the n-GaN region, resulting in a reduced electron over flow and enhanced the current spreading horizontally in the n- GaN region. These lead to increased optical output power and external quantum efficiency (EQE) from the proposed device.

Low thermal-mass LEDs: size effect and limits.

In this work, low thermal-mass LEDs (LTM-LEDs) were developed and demonstrated in flip-chip configuration, studying both experimentally and theoretically the enhanced electrical and optical characteristics and the limits. LTM-LED chips in 25 × 25 µm2, 50 × 50 µm2, 100 × 100 µm2 and 200 × 200 µm2 mesa sizes were fabricated and comparatively investigated. Here it was revealed that both the electrical and optical properties are improved by the decreasing chip size due to the reduced thermal mass. With a smaller chip size (from 200 µm to 50 µm), the device generally presents higher current density against the bias and higher power density against the current density. However, the 25 × 25 µm2 device behaves differently, limited by the fabrication margin limit of 10 µm. The underneath mechanisms of these observations are uncovered, and furthermore, based on the device model, it is proven that for a specific flip-chip fabrication process, the ideal size for LTM-LEDs with optimal power density performance can be identified.