Observation of field emission from GeSn nanoparticles epitaxially grown on silicon nanopillar arrays.

We apply molecular beam epitaxy to grow GeSn-nanoparticles on top of Si-nanopillars patterned onto p-type Si wafers. We use x-ray photoelectron spectroscopy to confirm a metallic behavior of the nanoparticle surface due to partial Sn segregation as well as the presence of a superficial Ge oxide. We report the observation of stable field emission (FE) current from the GeSn-nanoparticles, with turn on field of [Formula: see text] and field enhancement factor ߠ∼ 100 at anode-cathode distance of ∼0.6 µm. We prove that FE can be enhanced by preventing GeSn nanoparticles oxidation or by breaking the oxide layer through electrical stress. Finally, we show that GeSn/p-Si junctions have a rectifying behavior.

Selective Epitaxy of InP on Si and Rectification in Graphene/InP/Si Hybrid Structure.

The epitaxial integration of highly heterogeneous material systems with silicon (Si) is a central topic in (opto-)electronics owing to device applications. InP could open new avenues for the realization of novel devices such as high-mobility transistors in next-generation CMOS or efficient lasers in Si photonics circuitry. However, the InP/Si heteroepitaxy is highly challenging due to the lattice (∼8%), thermal expansion mismatch (∼84%), and the different lattice symmetries. Here, we demonstrate the growth of InP nanocrystals showing high structural quality and excellent optoelectronic properties on Si. Our CMOS-compatible innovative approach exploits the selective epitaxy of InP nanocrystals on Si nanometric seeds obtained by the opening of lattice-arranged Si nanotips embedded in a SiO2 matrix. A graphene/InP/Si-tip heterostructure was realized on obtained materials, revealing rectifying behavior and promising photodetection. This work presents a significant advance toward the monolithic integration of graphene/III-V based hybrid devices onto the mainstream Si technology platform.

Perfluorodecyltrichlorosilane-based seed-layer for improved chemical vapour deposition of ultrathin hafnium dioxide films on graphene.

We investigate the use of perfluorodecyltrichlorosilane-based self-assembled monolayer as seeding layer for chemical vapour deposition of HfO2 on large area CVD graphene. The deposition and evolution of the FDTS-based seed layer is investigated by X-ray photoelectron spectroscopy, Auger electron spectroscopy, and transmission electron microscopy. Crystalline quality of graphene transferred from Cu is monitored during formation of the seed layer as well as the HfO2 growth using Raman spectroscopy. We demonstrate that FDTS-based seed layer significantly improves nucleation of HfO2 layers so that graphene can be coated in a conformal way with HfO2 layers as thin as 10 nm. Proof-of-concept experiments on 200 mm wafers presented here validate applicability of the proposed approach to wafer scale graphene device fabrication.

Graphene growth on Ge(100)/Si(100) substrates by CVD method.

The successful integration of graphene into microelectronic devices is strongly dependent on the availability of direct deposition processes, which can provide uniform, large area and high quality graphene on nonmetallic substrates. As of today the dominant technology is based on Si and obtaining graphene with Si is treated as the most advantageous solution. However, the formation of carbide during the growth process makes manufacturing graphene on Si wafers extremely challenging. To overcome these difficulties and reach the set goals, we proposed growth of high quality graphene layers by the CVD method on Ge(100)/Si(100) wafers. In addition, a stochastic model was applied in order to describe the graphene growth process on the Ge(100)/Si(100) substrate and to determine the direction of further processes. As a result, high quality graphene was grown, which was proved by Raman spectroscopy results, showing uniform monolayer films with FWHM of the 2D band of 32 cm(-1).

Photodetection in Hybrid Single-Layer Graphene/Fully Coherent Germanium Island Nanostructures Selectively Grown on Silicon Nanotip Patterns.

Dislocation networks are one of the most principle sources deteriorating the performances of devices based on lattice-mismatched heteroepitaxial systems. We demonstrate here a technique enabling fully coherent germanium (Ge) islands selectively grown on nanotip-patterned Si(001) substrates. The silicon (Si)-tip-patterned substrate, fabricated by complementary metal oxide semiconductor compatible nanotechnology, features ∼50-nm-wide Si areas emerging from a SiO2 matrix and arranged in an ordered lattice. Molecular beam epitaxy growths result in Ge nanoislands with high selectivity and having homogeneous shape and size. The ∼850 °C growth temperature required for ensuring selective growth has been shown to lead to the formation of Ge islands of high crystalline quality without extensive Si intermixing (with 91 atom % Ge). Nanotip-patterned wafers result in geometric, kinetic-diffusion-barrier intermixing hindrance, confining the major intermixing to the pedestal region of Ge islands, where kinetic diffusion barriers are, however, high. Theoretical calculations suggest that the thin Si/Ge layer at the interface plays, nevertheless, a significant role in realizing our fully coherent Ge nanoislands free from extended defects especially dislocations. Single-layer graphene/Ge/Si-tip Schottky junctions were fabricated, and thanks to the absence of extended defects in Ge islands, they demonstrate high-performance photodetection characteristics with responsivity of ∼45 mA W(-1) and an Ion/Ioff ratio of ∼10(3).

Graphene field effect transistors with niobium contacts and asymmetric transfer characteristics.

We fabricate back-gated field effect transistors using niobium electrodes on mechanically exfoliated monolayer graphene and perform electrical characterization in the pressure range from atmospheric down to 10(-4) mbar. We study the effect of room temperature vacuum degassing and report asymmetric transfer characteristics with a resistance plateau in the n-branch. We show that weakly chemisorbed Nb acts as p-dopant on graphene and explain the transistor characteristics by Nb/graphene interaction with unpinned Fermi level at the interface.

Residual metallic contamination of transferred chemical vapor deposited graphene.

Integration of graphene with Si microelectronics is very appealing by offering a potentially broad range of new functionalities. New materials to be integrated with the Si platform must conform to stringent purity standards. Here, we investigate graphene layers grown on copper foils by chemical vapor deposition and transferred to silicon wafers by wet etching and electrochemical delamination methods with respect to residual submonolayer metallic contaminations. Regardless of the transfer method and associated cleaning scheme, time-of-flight secondary ion mass spectrometry and total reflection X-ray fluorescence measurements indicate that the graphene sheets are contaminated with residual metals (copper, iron) with a concentration exceeding 10(13) atoms/cm(2). These metal impurities appear to be partially mobile upon thermal treatment, as shown by depth profiling and reduction of the minority charge carrier diffusion length in the silicon substrate. As residual metallic impurities can significantly alter electronic and electrochemical properties of graphene and can severely impede the process of integration with silicon microelectronics, these results reveal that further progress in synthesis, handling, and cleaning of graphene is required to advance electronic and optoelectronic applications.

A graphene-based hot electron transistor.

We experimentally demonstrate DC functionality of graphene-based hot electron transistors, which we call graphene base transistors (GBT). The fabrication scheme is potentially compatible with silicon technology and can be carried out at the wafer scale with standard silicon technology. The state of the GBTs can be switched by a potential applied to the transistor base, which is made of graphene. Transfer characteristics of the GBTs show ON/OFF current ratios exceeding 10(4).

Charge transfer and partial pinning at the contacts as the origin of a double dip in the transfer characteristics of graphene-based field-effect transistors.

We discuss the origin of an additional dip other than the charge neutrality point observed in the transfer characteristics of graphene-based field-effect transistors with a Si/SiO2 substrate used as the back-gate. The double dip is proved to arise from charge transfer between the graphene and the metal electrodes, while charge storage at the graphene/SiO2 interface can make it more evident. Considering a different Fermi energy from the neutrality point along the channel and partial charge pinning at the contacts, we propose a model which explains all the features observed in the gate voltage loops. We finally show that the double dip enhanced hysteresis in the transfer characteristics can be exploited to realize graphene-based memory devices.