Overview of Memristor-Based Design for Analog Applications.

Memristor-based design has gained significant attention in recent years due to its potential to revolutionize various fields such as artificial intelligence, neuromorphic computing, non-volatile memory, signal processing, filtering, and radio frequency design. These emerging devices offer unique advantages such as non-volatile memory, low power consumption, and a high integration density. Their scalability and compatibility with existing fabrication processes make them an attractive option for industry adoption, paving the way for faster and more efficient architecture design. Researchers are actively exploring ways to optimize memristor technology for practical applications to harness its full potential. This includes developing novel materials and structures as well as improving the reliability and performance of memristors in various applications. This paper provides a comprehensive overview of the current advancements in memristor technology and their potential impact on the design of future electronic systems, focusing on its applications in the analog domain. By exploring the latest research and development in this field, researchers can gain valuable insights into how analog memristors can be integrated into their designs to achieve enhanced performance and efficiency. The paper delves into the fundamental principles of memristor technology, exploring its unique characteristics and advantages over traditional electronic components. It discusses the potential impact of memristors and challenges in the analog field of electronics, and highlights the progress made in their integration with existing circuitry, enabling novel functionalities and improved performance. Furthermore, it highlights ongoing research efforts to improve the performance and reliability of memristors, as well as the potential limitations and challenges that need to be addressed for widespread adoption, including variability in performance and reliability.

High-Speed Hardware Architecture Based on Error Detection for KECCAK.

The hash function KECCAK integrity algorithm is implemented in cryptographic systems to provide high security for any circuit requiring integrity and protect the transmitted data. Fault attacks, which can extricate confidential data, are one of the most effective physical attacks against KECCAK hardware. Several KECCAK fault detection systems have been proposed to counteract fault attacks. The present research proposes a modified KECCAK architecture and scrambling algorithm to protect against fault injection attacks. Thus, the KECCAK round is modified so that it consists of two parts with input and pipeline registers. The scheme is independent of the KECCAK design. Iterative and pipeline designs are both protected by it. To test the resilience of the suggested detection system approach fault attacks, we conduct permanent as well as transient fault attacks, and we evaluate the fault detection capabilities (99.9999% for transient faults and 99.999905% for permanent faults). The KECCAK fault detection scheme is modeled using VHDL language and implemented on an FPGA hardware board. The experimental results show that our technique effectively secures the KECCAK design. It can be carried out with little difficulty. In addition, the experimental FPGA results demonstrate the proposed KECCAK detection scheme's low area burden, high efficiency and working frequency.