The sodium ion-assisted memory behaviour of a silicon nanowire partial composite field-effect transistor.

A partial composite consisting of rough silicon nanowires and a polymer dielectric layer with sufficient Na(+) ions was used to create a field-effect transistor based memory device. Addition of Na(+) ions helped compensate for water molecule trapped charges leading to narrow hysteresis characteristics and stable memory retention stability of the resulting device.

White light emission from heterojunction diodes based on surface-oxidized porous Si nanowire arrays and amorphous In-Ga-Zn-O capping.

A novel heterojunction white light emitting diode (LED) structure based on an array of vertically aligned surface-passivated p-type porous Si nanowires (PSiNWs) with n-type amorphous In-Ga-Zn-O (a-IGZO) capping is introduced. PSiNWs were initially synthesized by electroless etching of p-type Si (100) wafers assisted by Ag nanoparticle catalysts and then surface-passivated by thermal oxidation. The nanowires synthesized by metal-assisted electroless etching were found to have longitudinally varying nanoporous morphologies due to differences in the duration of exposure to etching environment. These PSiNWs were optically active with orange red photoluminescence consisting of dark red to yellow emissions attributable to quantum confinement effects and to modified band structures. The LED structures emitted visible white light while exhibiting rectifying current-voltage characteristics. The white light emission was found to be the result of the combination of dark red to yellow emissions originating from the quantum confinement effect within the PSiNWs and green to blue emissions due to the oxygen-deficiency-related recombination centers introduced during the surface oxidation.

A route for modulating the diameter of cylindrical silicon nanowires by using thermal self-ordering silver nanoparticles.

For the synthesis of uniform sub-80-nm silicon nanowires (Si NWs), we introduce a metal-assisted chemical etching (MCE)-based facile and high-yield route, employing simple thermal annealing and vacuum deposition processes. Under rapid thermal annealing, an ultrathin silver (Ag) film on a Si substrate is self-organized into Ag nanoparticles (NPs), which are used for making Si nanoholes through a short MCE process. After sputter deposition of Au (10 nm)/Ag (20 nm) on the caved Si substrate with nanoholes, a nanomesh is obtained. Finally, with the nanomesh as an etching mask, Si NWs are successfully produced through a second MCE process. The size of the Si NWs can be modulated by controlling the thickness of the initial Ag film. The minimum diameter of the synthesized Si NWs is 30 ± 5 nm, and the maximum diameter is 68 ± 10 nm. Furthermore, to determine the uniformity of our Si NWs, bottom-gate field-effect transistors were fabricated and the linearity of the on-current level of these transistors with the number of addressed Si NWs was confirmed.

Effects of solution temperature on solution-processed high-performance metal oxide thin-film transistors.

Herein, we report a novel and easy strategy for fabricating solution-processed metal oxide thin-film transistors by controlling the dielectric constant of H2O through manipulation of the metal precursor solution temperature. As a result, indium zinc oxide (IZO) thin-film transistors (TFTs) fabricated from IZO solution at 4 °C can be operated after annealing at low temperatures (∼250 °C). In contrast, IZO TFTs fabricated from IZO solutions at 25 and 60 °C must be annealed at 275 and 300 °C, respectively. We also found that IZO TFTs fabricated from the IZO precursor solution at 4 °C had the highest mobility of 12.65 cm2/(V s), whereas the IZO TFTs fabricated from IZO precursor solutions at 25 and 60 °C had field-effect mobility of 5.39 and 4.51 cm2/(V s), respectively, after annealing at 350 °C. When the IZO precursor solution is at 4 °C, metal cations such as indium (In3+) and zinc ions (Zn2+) can be fully surrounded by H2O molecules, because of the higher dielectric constant of H2O at lower temperatures. These chemical complexes in the IZO precursor solution at 4 °C are advantageous for thermal hydrolysis and condensation reactions yielding a metal oxide lattice, because of their high potential energies. The IZO TFTs fabricated from the IZO precursor solution at 4 °C had the highest mobility because of the formation of many metal-oxygen-metal (M-O-M) bonds under these conditions. In these bonds, the ns-orbitals of the metal cations overlap each other and form electron conduction pathways. Thus, the formation of a high proportion of M-O-M bonds in the IZO thin films is advantageous for electron conduction, because oxide lattices allow electrons to travel easily through the IZO.

Mode tunable p-type Si nanowire transistor based zero drive load logic inverter.

A design platform for a zero drive load logic inverter consisting of p-channel Si nanowire based transistors, which controlled their operating mode through an implantation into a gate dielectric layer was demonstrated. As a result, a nanowire based class D inverter having a 4.6 gain value at V(DD) of -20 V was successfully fabricated on a substrate.

One-dimensional semiconductor nanostructure based thin-film partial composite formed by transfer implantation for high-performance flexible and printable electronics at low temperature.

Having high bending stability and effective gate coupling, the one-dimensional semiconductor nanostructures (ODSNs)-based thin-film partial composite was demonstrated, and its feasibility was confirmed through fabricating the Si NW thin-film partial composite on the poly(4-vinylphenol) (PVP) layer, obtaining uniform and high-performance flexible field-effect transistors (FETs). With the thin-film partial composite optimized by controlling the key steps consisting of the two-dimensional random dispersion on the hydrophilic substrate of ODSNs and the pressure-induced transfer implantation of them into the uncured thin dielectric polymer layer, the multinanowire (NW) FET devices were simply fabricated. As the NW density increases, the on-current of NW FETs increases linearly, implying that uniform NW distribution can be obtained with random directions over the entire region of the substrate despite the simplicity of the drop-casting method. The implantation of NWs by mechanical transfer printing onto the PVP layer enhanced the gate coupling and bending stability. As a result, the enhancements of the field-effect mobility and subthreshold swing and the stable device operation up to a 2.5 mm radius bending situation were achieved without an additional top passivation.

Programmable direct-printing nanowire electronic components.

In order for recently developed advanced nanowire (NW) devices(1-5) to be produced on a large scale, high integration of the separately fabricated nanoscale devices into intentionally organized systems is indispensible. We suggest a unique fabrication route for semiconductor NW electronics. This route provides a high yield and a large degree of freedom positioning the device on the substrate. Hence, we can achieve not only a uniform performance of Si NW devices with high fabrication yields, suppressing device-to-device variation, but also programmable integration of the NWs. Here, keeping pace with recent progress of direct-writing circuitry,(6-8) we show the flexibility of our approach through the individual integrating, along with the three predesigned N-shaped sites. On each predesigned site, nine bottom gate p-type Si NW field-effect transistors classified according to their on-current level are programmably integrated.