A Supervised Learning Algorithm for Multilayer Spiking Neural Networks Based on Temporal Coding Toward Energy-Efficient VLSI Processor Design.

Spiking neural networks (SNNs) are brain-inspired mathematical models with the ability to process information in the form of spikes. SNNs are expected to provide not only new machine-learning algorithms but also energy-efficient computational models when implemented in very-large-scale integration (VLSI) circuits. In this article, we propose a novel supervised learning algorithm for SNNs based on temporal coding. A spiking neuron in this algorithm is designed to facilitate analog VLSI implementations with analog resistive memory, by which ultrahigh energy efficiency can be achieved. We also propose several techniques to improve the performance on recognition tasks and show that the classification accuracy of the proposed algorithm is as high as that of the state-of-the-art temporal coding SNN algorithms on the MNIST and Fashion-MNIST datasets. Finally, we discuss the robustness of the proposed SNNs against variations that arise from the device manufacturing process and are unavoidable in analog VLSI implementation. We also propose a technique to suppress the effects of variations in the manufacturing process on the recognition performance.

A shared synapse architecture for efficient FPGA implementation of autoencoders.

This paper proposes a shared synapse architecture for autoencoders (AEs), and implements an AE with the proposed architecture as a digital circuit on a field-programmable gate array (FPGA). In the proposed architecture, the values of the synapse weights are shared between the synapses of an input and a hidden layer, and between the synapses of a hidden and an output layer. This architecture utilizes less of the limited resources of an FPGA than an architecture which does not share the synapse weights, and reduces the amount of synapse modules used by half. For the proposed circuit to be implemented into various types of AEs, it utilizes three kinds of parameters; one to change the number of layers' units, one to change the bit width of an internal value, and a learning rate. By altering a network configuration using these parameters, the proposed architecture can be used to construct a stacked AE. The proposed circuits are logically synthesized, and the number of their resources is determined. Our experimental results show that single and stacked AE circuits utilizing the proposed shared synapse architecture operate as regular AEs and as regular stacked AEs. The scalability of the proposed circuit and the relationship between the bit widths and the learning results are also determined. The clock cycles of the proposed circuits are formulated, and this formula is used to estimate the theoretical performance of the circuit when the circuit is used to construct arbitrary networks.

Experimental distinction between chaotic and strange nonchaotic attractors on the basis of consistency.

We experimentally study strange nonchaotic attractors (SNAs) and chaotic attractors by using a nonlinear integrated circuit driven by a quasiperiodic input signal. An SNA is a geometrically strange attractor for which typical orbits have nonpositive Lyapunov exponents. It is a difficult problem to distinguish between SNAs and chaotic attractors experimentally. If a system has an SNA as a unique attractor, the system produces an identical response to a repeated quasiperiodic signal, regardless of the initial conditions, after a certain transient time. Such reproducibility of response outputs is called consistency. On the other hand, if the attractor is chaotic, the consistency is low owing to the sensitive dependence on initial conditions. In this paper, we analyze the experimental data for distinguishing between SNAs and chaotic attractors on the basis of the consistency.

A multi-nano-dot circuit and structure using thermal-noise-assisted tunneling for stochastic associative processing.

The single-electron circuit and nanostructure described in this paper are designed for stochastic associative processing, which is an expanded version of ordinary associative memory processing. In stochastic associative processing, the association probability of each stored pattern depends on the similarity between the stored pattern and the input pattern. Such unique processing is useful for sequential stochastic association and for clustering for vector quantization. Conventional single-electron circuits operate only at very low temperature for practical junction capacitance (i.e., 30 K for 0.1 aF) because the charging energy in these circuits is directly related to the tunnel junction capacitance. Our multi-nano-dot circuit and structure operate at room temperature with a junction capacitance around 0.1 aF through tunneling processes assisted by thermal noise. We analyze the operation of this circuit in detail and propose for it a stochastic associative processing operation, where the detection timing of the electron position controls the association probability distribution.