Burst-mode optical label processor with ultralow power consumption.

A novel label processor subsystem for 100-Gbps (25-Gbps × 4λs) burst-mode optical packets is developed, in which a highly energy-efficient method is pursued for extracting and interfacing the ultrafast packet-label to a CMOS-based processor where label recognition takes place. The method involves performing serial-to-parallel conversion for the label bits on a bit-by-bit basis by using an optoelectronic converter that is operated with a set of optical triggers generated in a burst-mode manner upon packet arrival. Here we present three key achievements that enabled a significant reduction in the total power consumption and latency of the whole subsystem; 1) based on a novel operation mechanism for providing amplification with bit-level selectivity, an optical trigger pulse generator, that consumes power for a very short duration upon packet arrival, is proposed and experimentally demonstrated, 2) the energy of optical triggers needed by the optoelectronic serial-to-parallel converter is reduced by utilizing a negative-polarity signal while employing an enhanced conversion scheme entitled the discharge-or-hold scheme, 3) the necessary optical trigger energy is further cut down by half by coupling the triggers through the chip's backside, whereas a novel lens-free packaging method is developed to enable a low-cost alignment process that works with simple visual observation.

A novel optoelectronic serial-to-parallel converter for 25-Gbps burst-mode optical packets.

A new optoelectronic serial-to-parallel converter (SPC) has been developed to interface 25-Gbps asynchronous optical packets to CMOS circuitry. Other than all previous optoelectronic SPCs that are limited to single-shot operation and hence that can only be used for packet label processing, the SPC presented here can operate repeatedly with a period of as low as 640 ps to perform 1:16 conversion for an entire burst-mode 25-Gbps optical packet. The new SPC adopts a shared-trigger configuration and hence a single device can either convert a single packet or dual packets simultaneously. In this paper, the design and operation of the new SPC is explained after reviewing the fundamentals of performing bit-by-bit serial-to-parallel conversion by using HEMT-arrays and MSM-PDs. The response of the fabricated SPC device is presented and explained, together with the experimental work done to demonstrate 1:16 dual packet conversion at 25 Gbps.

Self-stabilizing optical clock pulse-train generator using SOA and saturable absorber for asynchronous optical packet processing.

We propose a novel, self-stabilizing optical clock pulse-train generator for processing preamble-free, asynchronous optical packets with variable lengths. The generator is based on an optical loop that includes a semiconductor optical amplifier (SOA) and a high-extinction spin-polarized saturable absorber (SA), with the loop being self-stabilized by balancing out the gain and absorption provided by the SOA and SA, respectively. The optical pulse train is generated by tapping out a small portion of a circulating seed pulse. The convergence of the generated pulse energy is enabled by the loop round-trip gain function that has a negative slope due to gain saturation in the SOA. The amplified spontaneous emission (ASE) of the SOA is effectively suppressed by the SA, and a backward optical pulse launched into the SOA enables overcoming the carrier-recovery speed mismatch between the SOA and SA. Without external control for the loop gain, a stable optical pulse train consisting of more than 50 pulses with low jitter is generated from a single 10-ps seed optical pulse even with a variation of 10 dB in the seed pulse intensity.

Enhanced multi-hop operation using hybrid optoelectronic router with time-to-live-based selective forward error correction.

Multi-hop operation is demonstrated with a prototype hybrid optoelectronic router for optical packet switched networks. The router is realized by combining key optical/optoelectronic device/sub-system technologies and complementary metal-oxide-semiconductor electronics. Using the hop count monitored via the time-to-live field in the packet label, the optoelectronic buffer of the router performs buffering with forward error correction selectively for packets degraded due to multiple hopping every N hops. Experimental results for 10-Gb/s optical packets confirm that the scheme can expand the number of hops while keeping the bit error rate low without the need for optical 3R regenerators at each node.

Hybrid optoelectronic buffer using CMOS memory and optical interfaces for 10-Gbit/s asynchronous variable-length optical packets.

A hybrid optoelectronic buffer consisting of a complementary metal-oxide-semiconductor (CMOS) memory and optical/optoelectronic interface devices is described. The interface devices: an all-optical serial-to-parallel converter (SPC), electrical-to-optical parallel-to-serial converter (PSC), and optical clock pulse-train generator (OCPTG) enable write-in/read-out of preamble-free asynchronous high-speed optical packets to/from CMOS memory, and consequently, flexible and highly functional processing of the packets with CMOS circuitry. A prototype hybrid optoelectronic buffer subsystem using a field programmable gate array (FPGA)-based memory and modules for the interface devices is developed and error-free write-in and read-out operation for 10-Gbit/s asynchronous variable-length optical packets is demonstrated.

4x4 optical packet switching of asynchronous burst optical packets with a prototype, 4x4 label processing and switching sub-system.

We report a prototype, 4x4 (4 input/4 output) label processing and switching sub-system for 10-Gb/s asynchronous burst variable-length optical packets. With the prototype, we perform a 4x4 optical packet switching demonstration, achieving error-free (BER<10(-12)) label processing and switching operation for all possible input/output combinations (16 switching paths) simultaneously. Power consumption and latency of the entire, self-contained sub-system is 83 W (includes fan power) and 300 ns, respectively.