Enhanced ZnO Thin-Film Transistor Performance Using Bilayer Gate Dielectrics.

We report ZnO TFTs using Al2O3/Ta2O5 bilayer gate dielectrics grown by atomic layer deposition. The saturation mobility of single layer Ta2O5 dielectric TFT was 0.1 cm(2) V(-1) s(-1), but increased to 13.3 cm(2) V(-1) s(-1) using Al2O3/Ta2O5 bilayer dielectric with significantly lower leakage current and hysteresis. We show that point defects present in ZnO film, particularly VZn, are the main reason for the poor TFT performance with single layer dielectric, although interfacial roughness scattering effects cannot be ruled out. Our approach combines the high dielectric constant of Ta2O5 and the excellent Al2O3/ZnO interface quality, resulting in improved device performance.

Indium-Free Fully Transparent Electronics Deposited Entirely by Atomic Layer Deposition.

Indium-free, fully transparent thin-film transistors are fabricated entirely by the atomic layer deposition technique on rigid and flexible substrates at a low temperature of 160 °C. The transistors show high saturation mobility, large switching ratio, and small subthreshold swing value. The inverters and ring oscillators show large gain value and small propagation delay time, indicating the potential of this process in transparent electronic devices.

Recent Developments in p-Type Oxide Semiconductor Materials and Devices.

The development of transparent p-type oxide semiconductors with good performance may be a true enabler for a variety of applications where transparency, power efficiency, and greater circuit complexity are needed. Such applications include transparent electronics, displays, sensors, photovoltaics, memristors, and electrochromics. Hence, here, recent developments in materials and devices based on p-type oxide semiconductors are reviewed, including ternary Cu-bearing oxides, binary copper oxides, tin monoxide, spinel oxides, and nickel oxides. The crystal and electronic structures of these materials are discussed, along with approaches to enhance valence-band dispersion to reduce effective mass and increase mobility. Strategies to reduce interfacial defects, off-state current, and material instability are suggested. Furthermore, it is shown that promising progress has been made in the performance of various types of devices based on p-type oxides. Several innovative approaches exist to fabricate transparent complementary metal oxide semiconductor (CMOS) devices, including novel device fabrication schemes and utilization of surface chemistry effects, resulting in good inverter gains. However, despite recent developments, p-type oxides still lag in performance behind their n-type counterparts, which have entered volume production in the display market. Recent successes along with the hurdles that stand in the way of commercial success of p-type oxide semiconductors are presented.

Low temperature processed complementary metal oxide semiconductor (CMOS) device by oxidation effect from capping layer.

In this report, both p- and n-type tin oxide thin-film transistors (TFTs) were simultaneously achieved using single-step deposition of the tin oxide channel layer. The tuning of charge carrier polarity in the tin oxide channel is achieved by selectively depositing a copper oxide capping layer on top of tin oxide, which serves as an oxygen source, providing additional oxygen to form an n-type tin dioxide phase. The oxidation process can be realized by annealing at temperature as low as 190 °C in air, which is significantly lower than the temperature generally required to form tin dioxide. Based on this approach, CMOS inverters based entirely on tin oxide TFTs were fabricated. Our method provides a solution to lower the process temperature for tin dioxide phase, which facilitates the application of this transparent oxide semiconductor in emerging electronic devices field.

Thin film complementary metal oxide semiconductor (CMOS) device using a single-step deposition of the channel layer.

We report, for the first time, the use of a single step deposition of semiconductor channel layer to simultaneously achieve both n- and p-type transport in transparent oxide thin film transistors (TFTs). This effect is achieved by controlling the concentration of hydroxyl groups (OH-groups) in the underlying gate dielectrics. The semiconducting tin oxide layer was deposited at room temperature, and the maximum device fabrication temperature was 350 °C. Both n and p-type TFTs showed fairly comparable performance. A functional CMOS inverter was fabricated using this novel scheme, indicating the potential use of our approach for various practical applications.

Record mobility in transparent p-type tin monoxide films and devices by phase engineering.

Here, we report the fabrication of nanoscale (15 nm) fully transparent p-type SnO thin film transistors (TFT) at temperatures as low as 180 °C with record device performance. Specifically, by carefully controlling the process conditions, we have developed SnO thin films with a Hall mobility of 18.71 cm(2) V(-1) s(-1) and fabricated TFT devices with a linear field-effect mobility of 6.75 cm(2) V(-1) s(-1) and 5.87 cm(2) V(-1) s(-1) on transparent rigid and translucent flexible substrates, respectively. These values of mobility are the highest reported to date for any p-type oxide processed at this low temperature. We further demonstrate that this high mobility is realized by careful phase engineering. Specifically, we show that phase-pure SnO is not necessarily the highest mobility phase; instead, well-controlled amounts of residual metallic tin are shown to substantially increase the hole mobility. A detailed phase stability map for physical vapor deposition of nanoscale SnO is constructed for the first time for this p-type oxide.

Impact of soft annealing on the performance of solution-processed amorphous zinc tin oxide thin-film transistors.

It is demonstrated that soft annealing duration strongly affects the performance of solution-processed amorphous zinc tin oxide thin-film transistors. Prolonged soft annealing times are found to induce two important changes in the device: (i) a decrease in zinc tin oxide film thickness, and (ii) an increase in oxygen vacancy concentration. The devices prepared without soft annealing exhibited inferior transistor performances, in comparison to devices in which the active channel layer (zinc tin oxide) was subjected to soft annealing. The highest saturation field-effect mobility-5.6 cm(2) V(-1) s(-1) with a drain-to-source on-off current ratio (Ion/Ioff) of 2 × 10(8)-was achieved in the case of devices with 10-min soft-annealed zinc tin oxide thin films as the channel layer. The findings of this work identify soft annealing as a critical parameter for the processing of chemically derived thin-film transistors, and it correlates device performance to the changes in material structure induced by soft annealing.

Solution-processable zinc oxide for the polymer solar cell based on P3HT:PCBM.

The device performance of polymer solar cells with zinc oxide (ZnO) nanoparticles inserted as an electron injection layer between the poly(3-hexylthiopene) (P3HT):phenyl-C60-butyric acid methyl ester (PCBM) active layer and the Al electrode was studied. The polymer solar cell consists of molybdenum-oxide (MoO3) as a hole injection layer, P3HT:PCBM bulk heterojunction as an active layer, and ZnO NPs as an electron injection layer. The ZnO layer was formed from a precursor solution on the top part of the P3HT:PCBM film (1:0.8 weight ratio) via sol-gel spin-coating, and was annealed at a low temperature (150 degrees C). The crystallinity, the atomic ratio of Zn and O, the absorption spectra, and the surface morphology of the ZnO thin films were studied. The device with a ZnO layer showed 9-11% higher J(SC) and 8-9% higher PCE compared to the devices without a ZnO layer. These improved device properties are attributed to the efficient electron extraction and the decreased reflectivity owing to the use of a ZnO layer.

Effect of cadmium arachidate layers on the growth of pentacene and the performance of pentacene-based thin film transistors.

The effect of cadmium arachidate (CdA) layers deposited by Langmuir-Blodgett technique on the growth of pentacene thin films and the performance of pentacene-based thin film transistors has been investigated. The hydrophobicity of the SiO2 gate dielectric surface was increased (surface energy reduced) with the deposition of CdA layers as a result of the presence of long hydrophobic alkyl chains attached to the cadmium atoms. The change in surface wetting properties of SiO2 strongly influenced the growth mechanism of pentacene thin films. The grain size and root-mean-square surface roughness of pentacene was decreased with an increase in the number of CdA layers compared to the pentacene deposited on a bare SiO2 surface. Organic thin film transistors (OTFTs) with seven layers of CdA on SiO2 showed the highest mobility of 0.27 cm2/Vs and the lowest subthreshold slope of 2.4 V/dec. The enhanced electrical properties of the OTFTs with SiO2/CdA as the dielectric is attributed to the better intermolecular connection, tight packing, and improved surface quality of the pentacene, as evident from the X-ray diffraction (XRD) and atomic force microscopy (AFM) results.