Analytical modelling of the transport in analog filamentary conductive-metal-oxide/HfOx ReRAM devices.

The recent co-optimization of memristive technologies and programming algorithms enabled neural networks training with in-memory computing systems. In this context, novel analog filamentary conductive-metal-oxide (CMO)/HfOx redox-based resistive switching memory (ReRAM) represents a key technology. Despite device performance enhancements reported in literature, the underlying mechanism behind resistive switching is not fully understood. This work presents the first physics-based analytical model of the current transport and of the resistive switching in these devices. As a case study, analog TaOx/HfOx ReRAM devices are considered. The current transport is explained by a trap-to-trap tunneling process, and the resistive switching by a modulation of the defect density within the sub-band of the TaOx that behaves as electric field and temperature confinement layer. The local temperature and electric field distributions are derived from the solution of the electric and heat transport equations in a 3D finite element ReRAM model. The intermediate resistive states are described as a gradual modulation of the TaOx defect density, which results in a variation of its electrical conductivity. The drift-dynamics of ions during the resistive switching is analytically described, allowing the estimation of defect migration energies in the TaOx layer. Moreover, the role of the electro-thermal properties of the CMO layer is unveiled. The proposed analytical model accurately describes the experimental switching characteristic of analog TaOx/HfOx ReRAM devices, increasing the physical understanding and providing the equations necessary for circuit simulations incorporating this technology.

A multi-timescale synaptic weight based on ferroelectric hafnium zirconium oxide.

Brain-inspired computing emerged as a forefront technology to harness the growing amount of data generated in an increasingly connected society. The complex dynamics involving short- and long-term memory are key to the undisputed performance of biological neural networks. Here, we report on sub-µm-sized artificial synaptic weights exploiting a combination of a ferroelectric space charge effect and oxidation state modulation in the oxide channel of a ferroelectric field effect transistor. They lead to a quasi-continuous resistance tuning of the synapse by a factor of 60 and a fine-grained weight update of more than 200 resistance values. We leverage a fast, saturating ferroelectric effect and a slow, ionic drift and diffusion process to engineer a multi-timescale artificial synapse. Our device demonstrates an endurance of more than 10 10 cycles, a ferroelectric retention of more than 10 years, and various types of volatility behavior on distinct timescales, making it well suited for neuromorphic and cognitive computing.

Neuromorphic Systems Design by Matching Inductive Biases to Hardware Constraints.

Neuromorphic systems are designed with careful consideration of the physical properties of the computational substrate they use. Neuromorphic engineers often exploit physical phenomena to directly implement a desired functionality, enabled by "the isomorphism between physical processes in different media" (Douglas et al., 1995). This bottom-up design methodology could be described as matching computational primitives to physical phenomena. In this paper, we propose a top-down counterpart to the bottom-up approach to neuromorphic design. Our top-down approach, termed "bias matching," is to match the inductive biases required in a learning system to the hardware constraints of its implementation; a well-known example is enforcing translation equivariance in a neural network by tying weights (replacing vector-matrix multiplications with convolutions), which reduces memory requirements. We give numerous examples from the literature and explain how they can be understood from this perspective. Furthermore, we propose novel network designs based on this approach in the context of collaborative filtering. Our simulation results underline our central conclusions: additional hardware constraints can improve the predictions of a Machine Learning system, and understanding the inductive biases that underlie these performance gains can be useful in finding applications for a given constraint.

Back-End, CMOS-Compatible Ferroelectric Field-Effect Transistor for Synaptic Weights.

Neuromorphic computing architectures enable the dense colocation of memory and processing elements within a single circuit. This colocation removes the communication bottleneck of transferring data between separate memory and computing units as in standard von Neuman architectures for data-critical applications including machine learning. The essential building blocks of neuromorphic systems are nonvolatile synaptic elements such as memristors. Key memristor properties include a suitable nonvolatile resistance range, continuous linear resistance modulation, and symmetric switching. In this work, we demonstrate voltage-controlled, symmetric and analog potentiation and depression of a ferroelectric Hf0.57Zr0.43O2 (HZO) field-effect transistor (FeFET) with good linearity. Our FeFET operates with low writing energy (fJ) and fast programming time (40 ns). Retention measurements have been performed over 4 bit depth with low noise (1%) in the tungsten oxide (WOx) readout channel. By adjusting the channel thickness from 15 to 8 nm, the on/off ratio of the FeFET can be engineered from 1 to 200% with an on-resistance ideally >100 kΩ, depending on the channel geometry. The device concept is using earth-abundant materials and is compatible with a back end of line (BEOL) integration into complementary metal-oxide-semiconductor (CMOS) processes. It has therefore a great potential for the fabrication of high-density, large-scale integrated arrays of artificial analog synapses.

Polymer waveguides for electro-optical integration in data centers and high-performance computers.

To satisfy the intra- and inter-system bandwidth requirements of future data centers and high-performance computers, low-cost low-power high-throughput optical interconnects will become a key enabling technology. To tightly integrate optics with the computing hardware, particularly in the context of CMOS-compatible silicon photonics, optical printed circuit boards using polymer waveguides are considered as a formidable platform. IBM Research has already demonstrated the essential silicon photonics and interconnection building blocks. A remaining challenge is electro-optical packaging, i.e., the connection of the silicon photonics chips with the system. In this paper, we present a new single-mode polymer waveguide technology and a scalable method for building the optical interface between silicon photonics chips and single-mode polymer waveguides.

Flip-chip optical couplers with scalable I/O count for silicon photonics.

A scalable and tolerant optical interfacing method based on flip-chip bonding is developed for silicon photonics packaging. Bidirectional optical couplers between multiple silicon-on-insulator waveguides and single-mode polymer waveguides are designed and fabricated. Successful operation is verified experimentally in the 1530-1570 nm spectral window. At the wavelength of 1570 nm, the coupling loss is as low as 0.8 dB for both polarization states and the planar misalignment loss is less than 0.6 dB for TE and 0.3 dB for TM polarization in a lateral silicon-polymer waveguide offset range of ± 2 µm. The coupling loss does not exhibit any temperature dependence up to the highest measurement point of 70°C.

Cascaded Mach-Zehnder wavelength filters in silicon photonics for low loss and flat pass-band WDM (de-)multiplexing.

We present 1-to-8 wavelength (de-)multiplexer devices based on a binary tree of cascaded Mach-Zehnder-like lattice filters, and manufactured using a 90 nm CMOS-integrated silicon photonics technology. We demonstrate that these devices combine a flat pass-band over more than 50% of the channel spacing with low insertion loss of less than 1.6 dB, and have a small device size of approximately 500 × 400 µm. This makes this type of filters well suited for application as WDM (de-)multiplexer in silicon photonics transceivers for optical data communication in large scale computer systems.