A third-order complementary metal-oxide-semiconductor sigma-delta modulator operating between 4.2 K and 300 K.

This paper presents a third-order switched-capacitor sigma-delta modulator implemented in a standard 0.35-µm CMOS process. It operates from 300 K down to 4.2 K, achieving 70.8 dB signal-to-noise-plus-distortion ratio (SNDR) in a signal bandwidth of 5 kHz with a sampling frequency of 500 kHz at 300 K. The modulator utilizes an operational transconductance amplifier in its loop filter, whose architecture has been optimized in order to eliminate the cryogenic anomalies below the freeze-out temperature. At 4.2 K, the modulator achieves 67.7 dB SNDR consuming 21.17 µA current from a 3.3 V supply.

A cryogenic analog to digital converter operating from 300 K down to 4.4 K.

This paper presents a cryogenic successive approximation register (SAR) based analog to digital converter (ADC) implemented in a standard 0.35 microm complementary metal oxide semiconductor (CMOS) process. It operates from room temperature down to 4.4 K, achieving 10.47 effective number of bits (ENOB) at room temperature. At 4.4 K, the ADC achieves 8.53 ENOB at 50 kS/s sampling rate with a current consumption of 90 microA from a 3.3 V supply. The ADC utilizes an improved comparator architecture, which performs offset cancellation by using preamplifiers designed for cryogenic operation. The conventional offset cancellation algorithm is also modified in order to eliminate the effect of cryogenic anomalies below freeze-out temperature. The power efficiency is significantly improved compared to the state of the art semiconductor ADCs operating in the same temperature range.