Recent Advances and Future Prospects for Memristive Materials, Devices, and Systems.

Memristive technology has been rapidly emerging as a potential alternative to traditional CMOS technology, which is facing fundamental limitations in its development. Since oxide-based resistive switches were demonstrated as memristors in 2008, memristive devices have garnered significant attention due to their biomimetic memory properties, which promise to significantly improve power consumption in computing applications. Here, we provide a comprehensive overview of recent advances in memristive technology, including memristive devices, theory, algorithms, architectures, and systems. In addition, we discuss research directions for various applications of memristive technology including hardware accelerators for artificial intelligence, in-sensor computing, and probabilistic computing. Finally, we provide a forward-looking perspective on the future of memristive technology, outlining the challenges and opportunities for further research and innovation in this field. By providing an up-to-date overview of the state-of-the-art in memristive technology, this review aims to inform and inspire further research in this field.

Electrochemical Ionic Synapses: Progress and Perspectives.

Artificial neural networks based on crossbar arrays of analog programmable resistors can address the high energy challenge of conventional hardware in artificial intelligence applications. However, state-of-the-art two-terminal resistive switching devices based on conductive filament formation suffer from high variability and poor controllability. Electrochemical ionic synapses are three-terminal devices that operate by electrochemical and dynamic insertion/extraction of ions that control the electronic conductivity of a channel in a single solid-solution phase. They are promising candidates for programmable resistors in crossbar arrays because they have shown uniform and deterministic control of electronic conductivity based on ion doping, with very low energy consumption. Here, the desirable specifications of these programmable resistors are presented. Then, an overview of the current progress of devices based on Li+ , O2- , and H+ ions and material systems is provided. Achieving nanosecond speed, low operation voltage (≈1 V), low energy consumption, with complementary metal-oxide-semiconductor compatibility all simultaneously remains a challenge. Toward this goal, a physical model of the device is constructed to provide guidelines for the desired material properties to overcome the remaining challenges. Finally, an outlook is provided, including strategies to advance materials toward the desirable properties and the future opportunities for electrochemical ionic synapses.

Self-heating hotspots in superconducting nanowires cooled by phonon black-body radiation.

Controlling thermal transport is important for a range of devices and technologies, from phase change memories to next-generation electronics. This is especially true in nano-scale devices where thermal transport is altered by the influence of surfaces and changes in dimensionality. In superconducting nanowire single-photon detectors, the thermal boundary conductance between the nanowire and the substrate it is fabricated on influences all of the performance metrics that make these detectors attractive for applications. This includes the maximum count rate, latency, jitter, and quantum efficiency. Despite its importance, the study of thermal boundary conductance in superconducting nanowire devices has not been done systematically, primarily due to the lack of a straightforward characterization method. Here, we show that simple electrical measurements can be used to estimate the thermal boundary conductance between nanowires and substrates and that these measurements agree with acoustic mismatch theory across a variety of substrates. Numerical simulations allow us to refine our understanding, however, open questions remain. This work should enable thermal engineering in superconducting nanowire electronics and cryogenic detectors for improved device performance.

Nanosecond protonic programmable resistors for analog deep learning.

Nanoscale ionic programmable resistors for analog deep learning are 1000 times smaller than biological cells, but it is not yet clear how much faster they can be relative to neurons and synapses. Scaling analyses of ionic transport and charge-transfer reaction rates point to operation in the nonlinear regime, where extreme electric fields are present within the solid electrolyte and its interfaces. In this work, we generated silicon-compatible nanoscale protonic programmable resistors with highly desirable characteristics under extreme electric fields. This operation regime enabled controlled shuttling and intercalation of protons in nanoseconds at room temperature in an energy-efficient manner. The devices showed symmetric, linear, and reversible modulation characteristics with many conductance states covering a 20× dynamic range. Thus, the space-time-energy performance of the all-solid-state artificial synapses can greatly exceed that of their biological counterparts.

Neural Network Training With Asymmetric Crosspoint Elements.

Analog crossbar arrays comprising programmable non-volatile resistors are under intense investigation for acceleration of deep neural network training. However, the ubiquitous asymmetric conductance modulation of practical resistive devices critically degrades the classification performance of networks trained with conventional algorithms. Here we first describe the fundamental reasons behind this incompatibility. Then, we explain the theoretical underpinnings of a novel fully-parallel training algorithm that is compatible with asymmetric crosspoint elements. By establishing a powerful analogy with classical mechanics, we explain how device asymmetry can be exploited as a useful feature for analog deep learning processors. Instead of conventionally tuning weights in the direction of the error function gradient, network parameters can be programmed to successfully minimize the total energy (Hamiltonian) of the system that incorporates the effects of device asymmetry. Our technique enables immediate realization of analog deep learning accelerators based on readily available device technologies.

CMOS-Compatible Protonic Programmable Resistor Based on Phosphosilicate Glass Electrolyte for Analog Deep Learning.

Ion intercalation based programmable resistors have emerged as a potential next-generation technology for analog deep-learning applications. Proton, being the smallest ion, is a very promising candidate to enable devices with high modulation speed, low energy consumption, and enhanced endurance. In this work, we report on the first back-end CMOS-compatible nonvolatile protonic programmable resistor enabled by the integration of phosphosilicate glass (PSG) as the proton solid electrolyte layer. PSG is an outstanding solid electrolyte material that displays both excellent protonic conduction and electronic insulation characteristics. Moreover, it is a well-known material within conventional Si fabrication, which enables precise deposition control and scalability. Our scaled all-solid-state three-terminal devices show desirable modulation characteristics in terms of symmetry, retention, endurance, and energy efficiency. Protonic programmable resistors based on phosphosilicate glass, therefore, represent promising candidates to realize nanoscale analog crossbar processors for monolithic CMOS integration.

Protonic solid-state electrochemical synapse for physical neural networks.

Physical neural networks made of analog resistive switching processors are promising platforms for analog computing. State-of-the-art resistive switches rely on either conductive filament formation or phase change. These processes suffer from poor reproducibility or high energy consumption, respectively. Herein, we demonstrate the behavior of an alternative synapse design that relies on a deterministic charge-controlled mechanism, modulated electrochemically in solid-state. The device operates by shuffling the smallest cation, the proton, in a three-terminal configuration. It has a channel of active material, WO3. A solid proton reservoir layer, PdHx, also serves as the gate terminal. A proton conducting solid electrolyte separates the channel and the reservoir. By protonation/deprotonation, we modulate the electronic conductivity of the channel over seven orders of magnitude, obtaining a continuum of resistance states. Proton intercalation increases the electronic conductivity of WO3 by increasing both the carrier density and mobility. This switching mechanism offers low energy dissipation, good reversibility, and high symmetry in programming.

Design and characterization of superconducting nanowire-based processors for acceleration of deep neural network training.

Training of deep neural networks (DNNs) is a computationally intensive task and requires massive volumes of data transfer. Performing these operations with the conventional von Neumann architectures creates unmanageable time and power costs. Recent studies have shown that mixed-signal designs involving resistive crossbar architectures are capable of achieving acceleration factors as high as 30 000 × over the state of the art digital processors. These approaches involve utilization of non-volatile memory elements as local processors. However, no technology has been developed to-date that can satisfy the strict device requirements for the unit cell. This paper presents the superconducting nanowire-based processing element as a crosspoint device. The unit cell has many programmable non-volatile states that can be used to perform analog multiplication. Importantly, these states are intrinsically discrete due to quantization of flux, which provides symmetric switching characteristics. Operation of these devices in a crossbar is described and verified with electro-thermal circuit simulations. Finally, validation of the concept in an actual DNN training task is shown using an emulator.

Single-Photon Single-Flux Coupled Detectors.

In this work, we present a novel device that is a combination of a superconducting nanowire single-photon detector and a superconducting multilevel memory. We show that these devices can be used to count the number of detections through single-photon to single-flux conversion. Electrical characterization of the memory properties demonstrates single-flux quantum (SFQ) separated states. Optical measurements using attenuated laser pulses with different mean photon number, pulse energies and repetition rates are shown to differentiate single-photon detection from other possible phenomena, such as multiphoton detection and thermal activation. Finally, different geometries and material stacks to improve device performance, as well as arraying methods, are discussed.

Training Deep Convolutional Neural Networks with Resistive Cross-Point Devices.

In a previous work we have detailed the requirements for obtaining maximal deep learning performance benefit by implementing fully connected deep neural networks (DNN) in the form of arrays of resistive devices. Here we extend the concept of Resistive Processing Unit (RPU) devices to convolutional neural networks (CNNs). We show how to map the convolutional layers to fully connected RPU arrays such that the parallelism of the hardware can be fully utilized in all three cycles of the backpropagation algorithm. We find that the noise and bound limitations imposed by the analog nature of the computations performed on the arrays significantly affect the training accuracy of the CNNs. Noise and bound management techniques are presented that mitigate these problems without introducing any additional complexity in the analog circuits and that can be addressed by the digital circuits. In addition, we discuss digitally programmable update management and device variability reduction techniques that can be used selectively for some of the layers in a CNN. We show that a combination of all those techniques enables a successful application of the RPU concept for training CNNs. The techniques discussed here are more general and can be applied beyond CNN architectures and therefore enables applicability of the RPU approach to a large class of neural network architectures.