A perspective on the physical scaling down of hafnia-based ferroelectrics.

HfO2-based ferroelectric thin films have attracted significant interest for semiconductor device applications due to their compatibility with complementary metal oxide semiconductor (CMOS) technology. One of the benefits of HfO2-based ferroelectric thin films is their ability to be scaled to thicknesses as low as 10 nm while retaining their ferroelectric properties; a feat that has been difficult to accomplish with conventional perovskite-based ferroelectrics using CMOS-compatible processes. However, reducing the thickness limit of HfO2-based ferroelectric thin films below the sub 5 nm thickness regime while preserving their ferroelectric property remains a formidable challenge. This is because both the structural factors of HfO2, including polymorphism and orientation, and the electrical factors of HfO2-based devices, such as the depolarization field, are known to be highly dependent on the HfO2thickness. Accordingly, when the thickness of HfO2drops below 5 nm, these factors will become even more crucial. In this regard, the size effect of HfO2-based ferroelectric thin films is thoroughly discussed in the present review. The impact of thickness on the ferroelectric property of HfO2-based thin films and the electrical performance of HfO2-based ferroelectric semiconductor devices, such as ferroelectric random-access-memory, ferroelectric field-effect-transistor, and ferroelectric tunnel junction, is extensively discussed from the perspective of fundamental theory and experimental results. Finally, recent developments and reports on achieving ferroelectric HfO2at sub-5 nm thickness regime and their applications are discussed.

Correction: Interfacial engineering of a Mo/Hf0.3Zr0.7O2/Si capacitor using the direct scavenging effect of a thin Ti layer.

Correction for 'Interfacial engineering of a Mo/Hf0.3Zr0.7O2/Si capacitor using the direct scavenging effect of a thin Ti layer' by Se Hyun Kim et al., Chem. Commun., 2021, 57, 12452-12455, https://doi.org/10.1039/D1CC04966F.

Revival of Ferroelectric Memories Based on Emerging Fluorite-Structured Ferroelectrics.

Over the last few decades, the research on ferroelectric memories has been limited due to their dimensional scalability and incompatibility with complementary metal-oxide-semiconductor (CMOS) technology. The discovery of ferroelectricity in fluorite-structured oxides revived interest in the research on ferroelectric memories, by inducing nanoscale nonvolatility in state-of-the-art gate insulators by minute doping and thermal treatment. The potential of this approach has been demonstrated by the fabrication of sub-30 nm electronic devices. Nonetheless, to realize practical applications, various technical limitations, such as insufficient reliability including endurance, retention, and imprint, as well as large device-to-device-variation, require urgent solutions. Furthermore, such limitations should be considered based on targeting devices as well as applications. Various types of ferroelectric memories including ferroelectric random-access-memory, ferroelectric field-effect-transistor, and ferroelectric tunnel junction should be considered for classical nonvolatile memories as well as emerging neuromorphic computing and processing-in-memory. Therefore, from the viewpoint of materials science, this review covers the recent research focusing on ferroelectric memories from the history of conventional approaches to future prospects.

Interfacial engineering of a Mo/Hf0.3Zr0.7O2/Si capacitor using the direct scavenging effect of a thin Ti layer.

An antiferroelectric Mo/Hf0.3Zr0.7O2/SIOx/Si capacitor was engineered using the direct scavenging effect of a sputtered Ti sacrificial layer. Charge trapping could be mitigated with the oxidized TiO2 layer, and the endurance could be enhanced beyond 109 cycles, which is higher than that of the gate stack of ferroelectric field-effect-transistors by 3-4 orders of magnitude.