Multimodal Encapsulation to Selectively Permeate Hydrogen and Engineer Channel Conduction for p-Type SnOx Thin-Film Transistor Applications.

It has been challenging to synthesize p-type SnOx (1 < x < 2) and engineer the electrical properties such as carrier density and mobility due to the narrow processing window and the localized oxygen 2p orbitals near the valence band. Herein, we report on the multifunctional encapsulation of p-SnOx to limit the surface adsorption of oxygen and selectively permeate hydrogen into the p-SnOx channel for thin-film transistor (TFT) applications. Time-of-flight secondary ion mass spectrometry (ToF-SIMS) measurements identified that ultrathin SiO2 as a multifunctional encapsulation layer effectively suppressed the oxygen adsorption on the back channel surface of p-SnOx and selectively diffused hydrogen across the entire thickness of the channel. Encapsulated p-SnOx-based TFTs demonstrated much enhanced channel conductance modulation in response to the gate bias applied, featuring higher on-state current and lower off-state current (on/off ratio > 103), field effect mobility of 3.41 cm2/(V s), and threshold voltages of ∼5-10 V. The fabricated devices show minimal deviations as small as ±6% in the TFT performance parameters, which demonstrates good reproducibility of the fabrication process. The relevance between the TFT performance and the effects of hydrogen permeation is discussed in regard to the intrinsic and extrinsic doping mechanisms. Density functional theory calculations reveal that hydrogen-related impurity complexes are in charge of the enhanced channel conductance with gate biases, which further supports the selective permeation of hydrogen through a thin SiO2 encapsulation.

Layer-resolved release of epitaxial layers in III-V heterostructure via a buffer-free mechanical separation technique.

Layer-release techniques for producing freestanding III-V epitaxial layers have been actively developed for heterointegration of single-crystalline compound semiconductors with Si platforms. However, for the release of target epitaxial layers from III-V heterostructures, it is required to embed a mechanically or chemically weak sacrificial buffer beneath the target layers. This requirement severely limits the scope of processable materials and their epi-structures and makes the growth and layer-release process complicated. Here, we report that epitaxial layers in commonly used III-V heterostructures can be precisely released with an atomic-scale surface flatness via a buffer-free separation technique. This result shows that heteroepitaxial interfaces of a normal lattice-matched III-V heterostructure can be mechanically separated without a sacrificial buffer and the target interface for separation can be selectively determined by adjusting process conditions. This technique of selective release of epitaxial layers in III-V heterostructures will provide high fabrication flexibility in compound semiconductor technology.

Simultaneous Extraction of the Grain Size, Single-Crystalline Grain Sheet Resistance, and Grain Boundary Resistivity of Polycrystalline Monolayer Graphene.

The electrical properties of polycrystalline graphene grown by chemical vapor deposition (CVD) are determined by grain-related parameters-average grain size, single-crystalline grain sheet resistance, and grain boundary (GB) resistivity. However, extracting these parameters still remains challenging because of the difficulty in observing graphene GBs and decoupling the grain sheet resistance and GB resistivity. In this work, we developed an electrical characterization method that can extract the average grain size, single-crystalline grain sheet resistance, and GB resistivity simultaneously. We observed that the material property, graphene sheet resistance, could depend on the device dimension and developed an analytical resistance model based on the cumulative distribution function of the gamma distribution, explaining the effect of the GB density and distribution in the graphene channel. We applied this model to CVD-grown monolayer graphene by characterizing transmission-line model patterns and simultaneously extracted the average grain size (~5.95 µm), single-crystalline grain sheet resistance (~321 Ω/sq), and GB resistivity (~18.16 kΩ-µm) of the CVD-graphene layer. The extracted values agreed well with those obtained from scanning electron microscopy images of ultraviolet/ozone-treated GBs and the electrical characterization of graphene devices with sub-micrometer channel lengths.

High-Performance Oxide-Based p-n Heterojunctions Integrating p-SnOx and n-InGaZnO.

The fabrication of oxide-based p-n heterojunctions that exhibit high rectification performance has been difficult to realize using standard manufacturing techniques that feature mild vacuum requirements, low thermal budget processing, and scalability. Critical bottlenecks in the fabrication of these heterojunctions include the narrow processing window of p-type oxides and the charge-blocking performance across the metallurgical junction required for achieving low reverse current and hence high rectification behavior. The overarching goal of the present study is to demonstrate a simple processing route to fabricate oxide-based p-n heterojunctions that demonstrate high on/off rectification behavior, a low saturation current, and a small turn-on voltage. For this study, room-temperature sputter-deposited p-SnOx and n-InGaZnO (IGZO) films were chosen. SnOx is a promising p-type oxide material due to its monocationic system that limits complexities related to processing and properties, compared to other multicationic oxide materials. For the n-type oxide, IGZO is selected due to the knowledge that postprocessing annealing critically reduces the defect and trap densities in IGZO to ensure minimal interfacial recombination and high charge-blocking performance in the heterojunctions. The resulting oxide p-n heterojunction exhibits a high rectification ratio greater than 103 at ±3 V, a low saturation current of ∼2 × 10-10 A, and a small turn-on voltage of ∼0.5 V. In addition, the demonstrated oxide p-n heterojunctions exhibit excellent stability over time in air due to the p-SnOx with completed reaction annealing in air and the reduced trap density in n-IGZO.

Effect of Graphene Doping Level near the Metal Contact Region on Electrical and Photoresponse Characteristics of Graphene Photodetector.

Graphene-metal contact is crucial to fabricate high-performance graphene photodetectors since the external quantum efficiency (EQE) of the photodetector depends on the contact properties, and the influence of the contact properties is particularly dominant in short channel devices for high-speed applications. Moreover, junction properties between the channel graphene and graphene near the contact are also important to analyze the photoresponse because the built-in electric field in the junction determines the EQE of the photodetector. In this study, we investigated a relation between the photoresponse and the built-in electric field induced from the doping level difference in the junction between the channel graphene and graphene near the contact. The photoresponse could be enhanced with a high junction barrier height that is tuned by the doping level difference. In addition, we observed that the improved electrical characteristics of channel graphene do not guarantee the enhancement of the photoresponse characteristics of graphene photodetectors.

Optimized poly(methyl methacrylate)-mediated graphene-transfer process for fabrication of high-quality graphene layer.

Graphene grown on a copper (Cu) substrate by chemical vapor deposition (CVD) is typically required to be transferred to another substrate for the fabrication of various electrical devices. PMMA-mediated wet process is the most widely used method for CVD-graphene-transfer. However, PMMA residue and wrinkles that inevitably remain on the graphene surface during the transfer process are critical issues degrading the electrical properties of graphene. In this paper, we report on a PMMA-mediated graphene-transfer method that can effectively reduce the density and size of the PMMA residue and the height of wrinkles on the transferred graphene layer. We found out that acetic acid is the most effective PMMA stripper among the typically used solutions to remove the PMMA residue. In addition, we observed that an optimized annealing process can reduce the height of the wrinkles on the transferred graphene layer without degrading the graphene quality. The effects of the suggested wet transfer process were also investigated by evaluating the electrical properties of field-effect transistors fabricated on the transferred graphene layer. The results of this work will contribute to the development of fabrication processes for high-quality graphene devices, given that the transfer of graphene from the Cu substrate is essential process to the application of CVD-graphene.