Controlled formation and resistivity scaling of nickel silicide nanolines.

We demonstrate a top-down method for fabricating nickel mono-silicide (NiSi) nanolines (also referred to as nanowires) with smooth sidewalls and line widths down to 15 nm. Four-probe electrical measurements reveal that the room temperature electrical resistivity of the NiSi nanolines remains constant as the line widths are reduced to 23 nm. The resistivity at cryogenic temperatures is found to increase with decreasing line width. This finding can be attributed to electron scattering at the sidewalls and is used to deduce an electron mean free path of 6.3 nm for NiSi at room temperature. The results suggest that NiSi nanolines with smooth sidewalls are able to meet the requirements for implementation at the 22 nm technology node without degradation of device performance.

Effects of strain gradients on strain measurements using geometrical phase analysis in the transmission electron microscope.

An analysis of the effects of lens aberrations on the phase contrast images used for strain measurement by geometric phase analysis (GPA) in the TEM shows that errors may result when strain gradients are present and when [formula: see text] at the reciprocal lattice spacing used for the analysis. This conclusion is demonstrated experimentally using a model specimen consisting of a strained Si layer grown epitaxially on a Si-Ge alloy substrate. Image simulations for this model specimen show that strain gradients can introduce oscillations in strain maps when the defocus is not optimized for GPA. This work also makes it possible to identify other potential sources of error in GPA.