New ray tracing method to investigate the various effects on wave propagation in medical scenario: an application of wireless body area network.

The advent of technology with the increasing use of wireless network has led to the development of Wireless Body Area Network (WBAN) to continuously monitor the change of physiological data in a cost efficient manner. As numerous researches on wave propagation characterization have been done in intrabody communication, this study has given emphasis on the wave propagation characterization between the control units (CUs) and wireless access point (AP) in a hospital scenario. Ray tracing is a tool to predict the rays to characterize the wave propagation. It takes huge simulation time, especially when multiple transmitters are involved to transmit physiological data in a realistic hospital environment. Therefore, this study has developed an accelerated ray tracing method based on the nearest neighbor cell and prior knowledge of intersection techniques. Beside this, Red-Black tree is used to store and provide a faster retrieval mechanism of objects in the hospital environment. To prove the superiority, detailed complexity analysis and calculations of reflection and transmission coefficients are also presented in this paper. The results show that the proposed method is about 1.51, 2.1, and 2.9 times faster than the Object Distribution Technique (ODT), Space Volumetric Partitioning (SVP), and Angular Z-Buffer (AZB) methods, respectively. To show the various effects on received power in 60 GHz frequency, few comparisons are made and it is found that on average -9.44 dBm, -8.23 dBm, and -9.27 dBm received power attenuations should be considered when human, AP, and CU move in a given hospital scenario.

Investigation of a novel common subexpression elimination method for low power and area efficient DCT architecture.

A wide interest has been observed to find a low power and area efficient hardware design of discrete cosine transform (DCT) algorithm. This research work proposed a novel Common Subexpression Elimination (CSE) based pipelined architecture for DCT, aimed at reproducing the cost metrics of power and area while maintaining high speed and accuracy in DCT applications. The proposed design combines the techniques of Canonical Signed Digit (CSD) representation and CSE to implement the multiplier-less method for fixed constant multiplication of DCT coefficients. Furthermore, symmetry in the DCT coefficient matrix is used with CSE to further decrease the number of arithmetic operations. This architecture needs a single-port memory to feed the inputs instead of multiport memory, which leads to reduction of the hardware cost and area. From the analysis of experimental results and performance comparisons, it is observed that the proposed scheme uses minimum logic utilizing mere 340 slices and 22 adders. Moreover, this design meets the real time constraints of different video/image coders and peak-signal-to-noise-ratio (PSNR) requirements. Furthermore, the proposed technique has significant advantages over recent well-known methods along with accuracy in terms of power reduction, silicon area usage, and maximum operating frequency by 41%, 15%, and 15%, respectively.