Improvement of Resistive Random Access Memory Device Performance via Embedding of Low-K Dielectric Layer.

The switching mechanisms of resistive random access memories (ReRAMs) were strongly related to the formation and rupture of conduction filaments (CFs) in the transition metal oxide (TMO) layer. The novel method approached to enhance the electrical characteristics of ReRAMs by introducing of the local insertion of the low-k dielectric layer inside the TMO layer. Simulation results showed that the insertion of the low-k dielectric layer in the TMO layer reduced the switching volume and the generation of CFs. The large variation of resistive switching properties was caused by the stochastic characteristics of the CFs, which was involved in switching by generation and rupture. The electrical characteristics of the novel ReRAMs exhibited a low reset current of below 20 microA, the high uniformity of the resistive switching, and the narrow variation of the resistance for the high resistance state.

Reliability Degeneration Mechanisms of the 20-nm Flash Memories Due to the Word Line Stress.

The electrical characteristics of NAND flash memories with a high-k dielectric layer were simulated by using a full three-dimensional technology computer-aided design simulator. The occurrence rate of the errors in the flash memories increases with increasing program/erase cycles. To verify the word line stress effect, electron density in the floating gate of target cell and non-target cell, the drain current in the channel of non-target cell and depletion region of the non-target cell were simulated as a function of program/erase cycle, for various floating gate thicknesses. The electron density in the floating gate became decreased with increasing program/erase cycles. The reliability degradation occured by the increased depletion region at the bottom of the polysilicon floating gate in the continued program/erase cycle situation due to the word line stress. The degradation mechanisms for the program characteristics of 20-nm NAND flash memories were clarified by examining electron density, darin current and depletion region.

Effect of the fixed charge distribution on the mobility degradation of the high-k dielectric MOSFETs.

The effects of the fixed charge in the high-k dielectric layer near a SiO2 layer on the mobility degradation mechanisms were investigated by using a full three-dimensional technology computer aided design simulator. The electron density and the electric field in the channel region were significantly affected due to the fixed charge in the SiO2 layer and the interface between SiO2 and HfO2 layers. The electron density in a channel increased with increasing fixed charge concentration, resulting in a decrease in the mobility. The variation of the vertical electric field due to the fixed charge in the high-k dielectric layer was attributed to the degradation effect. The electric field in a channel deteriorated the electron mobility due to the electron attraction to the heterointerface of the substrate and the interfacial layer. The mobility decreased with increasing fixed charge concentration near the heterointerface of the substrate and the SiO2 layer. The effect of the fixed charge distribution on the mobility degradation of the high-k dielectric MOSFETs was described on the simulation results.

Mobility degradation mechanisms of MOSFETs with a high-k dielectric layer.

The electrical characteristics of MOSFETs with a high-k dielectric layer were simulated by using a full three-dimensional technology computer-aided design simulator. The MOSFETs leakage current increased when their size decreased. The mobility variation mechanisms due to the polarization variation with the positive fixed charges in the high-k dielectric layer and with the negative trap charges in the SiO2 layer were clarified by using a modified mobility model of the universal model taking into account remote phonon scattering effects. The induced polarization in the high-k dielectric layer was dominantly attributed to the magnitude and the polarity of the charges in an interfacial layer. The mobility degradation was dominantly attributed to the polarization effects. The mobility values of the channel region in the MOSFETs, calculated by using the modified mobility model, were in reasonable agreement with their real mobility magnitudes. This result improves the enhancement of the electrical characteristic of the MOSFETs with a high-k layer.

Degradation mechanisms of the program characteristics of 10 nm NAND flash memories due to cell-to-cell interference.

The device characteristics of NAND flash memories with gate sizes from 14 to 32 nm were investigated by using a full three-dimensional technology computer-aided design simulator. Simulation results showed that the threshold voltage and the depletion regions of the floating gate (FG) of the 10-nm NAND flash memories increased with decreasing cell size. The electrical potential of the inter-poly-dielectric (IPD) surface and the tunneling layer surface decreased with increasing depletion region of the FG. The program characteristics of the 10-nm NAND flash memories decreased with decreasing electric potential on the IPD surface and the tunneling oxide surface. The electric field between the floating gate of the target cell and that of the neighboring cell increased with decreasing gate size due to a decrease in the distance between the two neighboring cells. The degradation mechanisms for the program characteristics of 10-nm NAND flash memories were clarified by changing the threshold voltage and the voltage shift.

Electrical characteristics of nanoscale NAND silicon-oxide-nitride-oxide-silicon flash memory devices fabricated on SOI substrates.

NAND silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices with double gates fabricated on silicon-on-insulator (SOI) substrates were proposed. The current-voltage characteristics related to the programming operation of the designed nanoscale NAND SONOS flash memory devices on a SOI substrate and on the conventional bulk-Si substrate were simulated and compared in order to investigate device characteristics of the scaled-down memory devices. The simulation results showed that the short channel effect and the subthreshod leakage current for the memory device with a large spacer length were lower than that of the memory device with a small spacer length due to increase of the effective channel length. The device performance of the memory device utilizing the SOI substrate exhibited a smaller subthreshold swing and a larger drain current level in comparison with those on the bulk-Si substrate. These improved electrical characteristices for the SOI devices could be explained by comparing the electric field distribution in a channel region for both devices.