Atomic fluctuations lifting the energy degeneracy in Si/SiGe quantum dots.

Electron spins in Si/SiGe quantum wells suffer from nearly degenerate conduction band valleys, which compete with the spin degree of freedom in the formation of qubits. Despite attempts to enhance the valley energy splitting deterministically, by engineering a sharp interface, valley splitting fluctuations remain a serious problem for qubit uniformity, needed to scale up to large quantum processors. Here, we elucidate and statistically predict the valley splitting by the holistic integration of 3D atomic-level properties, theory and transport. We find that the concentration fluctuations of Si and Ge atoms within the 3D landscape of Si/SiGe interfaces can explain the observed large spread of valley splitting from measurements on many quantum dot devices. Against the prevailing belief, we propose to boost these random alloy composition fluctuations by incorporating Ge atoms in the Si quantum well to statistically enhance valley splitting.

Quantum logic with spin qubits crossing the surface code threshold.

High-fidelity control of quantum bits is paramount for the reliable execution of quantum algorithms and for achieving fault tolerance-the ability to correct errors faster than they occur1. The central requirement for fault tolerance is expressed in terms of an error threshold. Whereas the actual threshold depends on many details, a common target is the approximately 1% error threshold of the well-known surface code2,3. Reaching two-qubit gate fidelities above 99% has been a long-standing major goal for semiconductor spin qubits. These qubits are promising for scaling, as they can leverage advanced semiconductor technology4. Here we report a spin-based quantum processor in silicon with single-qubit and two-qubit gate fidelities, all of which are above 99.5%, extracted from gate-set tomography. The average single-qubit gate fidelities remain above 99% when including crosstalk and idling errors on the neighbouring qubit. Using this high-fidelity gate set, we execute the demanding task of calculating molecular ground-state energies using a variational quantum eigensolver algorithm5. Having surpassed the 99% barrier for the two-qubit gate fidelity, semiconductor qubits are well positioned on the path to fault tolerance and to possible applications in the era of noisy intermediate-scale quantum devices.

CMOS-based cryogenic control of silicon quantum circuits.

The most promising quantum algorithms require quantum processors that host millions of quantum bits when targeting practical applications1. A key challenge towards large-scale quantum computation is the interconnect complexity. In current solid-state qubit implementations, an important interconnect bottleneck appears between the quantum chip in a dilution refrigerator and the room-temperature electronics. Advanced lithography supports the fabrication of both control electronics and qubits in silicon using technology compatible with complementary metal oxide semiconductors (CMOS)2. When the electronics are designed to operate at cryogenic temperatures, they can ultimately be integrated with the qubits on the same die or package, overcoming the 'wiring bottleneck'3-6. Here we report a cryogenic CMOS control chip operating at 3 kelvin, which outputs tailored microwave bursts to drive silicon quantum bits cooled to 20 millikelvin. We first benchmark the control chip and find an electrical performance consistent with qubit operations of 99.99 per cent fidelity, assuming ideal qubits. Next, we use it to coherently control actual qubits encoded in the spin of single electrons confined in silicon quantum dots7-9 and find that the cryogenic control chip achieves the same fidelity as commercial instruments at room temperature. Furthermore, we demonstrate the capabilities of the control chip by programming a number of benchmarking protocols, as well as the Deutsch-Josza algorithm10, on a two-qubit quantum processor. These results open up the way towards a fully integrated, scalable silicon-based quantum computer.

Author Correction: Rapid gate-based spin read-out in silicon using an on-chip resonator.

An amendment to this paper has been published and can be accessed via a link at the top of the paper.

Rapid gate-based spin read-out in silicon using an on-chip resonator.

Silicon spin qubits are one of the leading platforms for quantum computation1,2. As with any qubit implementation, a crucial requirement is the ability to measure individual quantum states rapidly and with high fidelity. Since the signal from a single electron spin is minute, the different spin states are converted to different charge states3,4. Charge detection, so far, has mostly relied on external electrometers5-7, which hinders scaling to two-dimensional spin qubit arrays2,8,9. Alternatively, gate-based dispersive read-out based on off-chip lumped element resonators has been demonstrated10-13, but integration times of 0.2-2 ms were required to achieve single-shot read-out14-16. Here, we connect an on-chip superconducting resonant circuit to two of the gates that confine electrons in a double quantum dot. Measurement of the power transmitted through a feedline coupled to the resonator probes the charge susceptibility, distinguishing whether or not an electron can oscillate between the dots in response to the probe power. With this approach, we achieve a signal-to-noise ratio of about six within an integration time of only 1 µs. Using Pauli's exclusion principle for spin-to-charge conversion, we demonstrate single-shot read-out of a two-electron spin state with an average fidelity of >98% in 6 µs. This result may form the basis of frequency-multiplexed read-out in dense spin qubit systems without external electrometers, therefore simplifying the system architecture.