Software implementation and hardware acceleration of retinal vessel segmentation for diabetic retinopathy screening tests.

Screening tests are an effective tool for the diagnosis and prevention of several diseases. Unfortunately, in order to produce an early diagnosis, the huge number of collected samples has to be processed faster than before. In particular this issue concerns image processing procedures, as they require a high computational complexity, which is not satisfied by modern software architectures. To this end, Field Programmable Gate Arrays (FPGAs) can be used to accelerate partially or entirely the computation. In this work, we demonstrate that the use of FPGAs is suitable for biomedical application, by proposing a case of study concerning the implementation of a vessels segmentation algorithm. The experimental results, computed on DRIVE and STARE databases, show remarkable improvements in terms of both execution time and power efficiency (6X and 5.7X respectively) compared to the software implementation. On the other hand, the proposed hardware approach outperforms literature works (3X speedup) without affecting the overall accuracy and sensitivity measures.

GPU-based computation for brain spatio-temporal networks definition.

Nowadays, with the increase of computational analysis in sciences such as biology and neuroscience, the computational aspect is one of the most challenging. The purpose of this work is the achieve the possibility to apply spatio-temporal networks inference techniques on brain to perform network analysis. One of the problems of spatio-temporal network applications is the computational time, and it becomes impractical to keep developing studies when it takes a long time to analyze and compute the results. We present a GPU-based system used to speed up the computation of spatio-temporal networks applied to different brain data; thanks to the architecture of these devices we are able to obtain an average increase in the performances of ~ 35× on a single GPU and ~ 78× on multi GPU with the respect of CPU execution.