Measurement of Exciton and Trion Energies in Multistacked hBN/WS2 Coupled Quantum Wells for Resonant Tunneling Diodes.

Quantum confinements, especially quantum in narrow wells, have been investigated because of their controllability over electrical parameters. For example, quantum dots can emit a variety of photon wavelengths even for the same material depending on their particle size. More recently, the research into two-dimensional (2D) materials has shown the availability of several quantum mechanical phenomenon confined within a sheet of materials. Starting with the gapless semimetal properties of graphene, current research has begun into the excitons and their properties within 2D materials. Even for simple 2D systems, experimental results often offer surprising results, unexpected from traditional studies. We investigated a coupled quantum well system using 2D hexagonal boron nitride (hBN) barrier as well as 2D tungsten disulfide (WS2) semiconductor arranged in stacked structures to study the various 2D to 2D interactions. We determined that for hexagonal boron nitride-tungsten disulfide (hBN/WS2) quantum well stacks, the interaction between successive wells resulted in decreasing bandgap, and the effect was pronounced even over a large distance of up to four stacks. Additionally, we observed that a single layer of isolating hBN barriers significantly reduces interlayer interaction between WS2 layers, while still preserving the interwell interactions in the alternative hBN/WS2 structure. The methods we used for the study of coupled quantum wells here show a method for determining the respective exciton energy levels and trion energy levels within 2D materials and 2D materials-based structures. Renormalization energy levels are the key in understanding conductive and photonic properties of stacked 2D materials.

Reliable Multivalued Conductance States in TaO x Memristors through Oxygen Plasma-Assisted Electrode Deposition with in Situ-Biased Conductance State Transmission Electron Microscopy Analysis.

Transition metal oxide-based memristors have widely been proposed for applications toward artificial synapses. In general, memristors have two or more electrically switchable stable resistance states that device researchers see as an analogue to the ion channels found in biological synapses. The mechanism behind resistive switching in metal oxides has been divided into electrochemical metallization models and valence change models. The stability of the resistance states in the memristor vary widely depending on: oxide material, electrode material, deposition conditions, film thickness, and programming conditions. So far, it has been extremely challenging to obtain reliable memristors with more than two stable multivalued states along with endurances greater than ∼1000 cycles for each of those states. Using an oxygen plasma-assisted sputter deposition method of noble metal electrodes, we found that the metal-oxide interface could be deposited with substantially lower interface roughness observable at the nanometer scale. This markedly improved device reliability and function, allowing for a demonstration of memristors with four completely distinct levels from ∼6 × 10-6 to ∼4 × 10-8 S that were tested up to 104 cycles per level. Furthermore through a unique in situ transmission electron microscopy study, we were able to verify a redox reaction-type model to be dominant in our samples, leading to the higher degree of electrical state controllability. For solid-state synapse applications, the improvements to electrical properties will lead to simple device structures, with an overall power and area reduction of at least 1000 times when compared to SRAM.

Enhancement of resistive switching under confined current path distribution enabled by insertion of atomically thin defective monolayer graphene.

Resistive random access memory (ReRAM) devices have been extensively investigated resulting in significant enhancement of switching properties. However fluctuations in switching parameters are still critical weak points which cause serious failures during 'reading' and 'writing' operations of ReRAM devices. It is believed that such fluctuations may be originated by random creation and rupture of conducting filaments inside ReRAM oxides. Here, we introduce defective monolayer graphene between an oxide film and an electrode to induce confined current path distribution inside the oxide film, and thus control the creation and rupture of conducting filaments. The ReRAM device with an atomically thin interlayer of defective monolayer graphene reveals much reduced fluctuations in switching parameters compared to a conventional one. Our results demonstrate that defective monolayer graphene paves the way to reliable ReRAM devices operating under confined current path distribution.

A plasma-treated chalcogenide switch device for stackable scalable 3D nanoscale memory.

Stackable select devices such as the oxide p-n junction diode and the Schottky diode (one-way switch) have been proposed for non-volatile unipolar resistive switching devices; however, bidirectional select devices (or two-way switch) need to be developed for bipolar resistive switching devices. Here we report on a fully stackable switching device that solves several problems including current density, temperature stability, cycling endurance and cycle distribution. We demonstrate that the threshold switching device based on As-Ge-Te-Si material significantly improves cycling endurance performance by reactive nitrogen deposition and nitrogen plasma hardening. Formation of the thin Si3N4 glass layer by the plasma treatment retards tellurium diffusion during cycling. Scalability of threshold switching devices is measured down to 30 nm scale with extremely fast switching speed of ~2 ns.

Graphene for true Ohmic contact at metal-semiconductor junctions.

The rectifying Schottky characteristics of the metal-semiconductor junction with high contact resistance have been a serious issue in modern electronic devices. Herein, we demonstrated the conversion of the Schottky nature of the Ni-Si junction, one of the most commonly used metal-semiconductor junctions, into an Ohmic contact with low contact resistance by inserting a single layer of graphene. The contact resistance achieved from the junction incorporating graphene was about 10(-8) ~ 10(-9) Ω cm(2) at a Si doping concentration of 10(17) cm(-3).

Transparent and flexible graphene charge-trap memory.

A transparent and flexible graphene charge-trap memory (GCTM) composed of a single-layer graphene channel and a 3-dimensional gate stack was fabricated on a polyethylene naphtalate substrate below eutectic temperatures (~110 °C). The GCTM exhibits memory functionality of ~8.6 V memory window and 30% data retention per 10 years, while maintaining ~80% of transparency in the visible wavelength. Under both tensile and compressive stress, the GCTM shows minimal effect on the program/erase states and the on-state current. This can be utilized for transparent and flexible electronics that require integration of logic, memory, and display on a single substrate with high transparency and endurance under flex.

Graphene barristor, a triode device with a gate-controlled Schottky barrier.

Despite several years of research into graphene electronics, sufficient on/off current ratio I(on)/I(off) in graphene transistors with conventional device structures has been impossible to obtain. We report on a three-terminal active device, a graphene variable-barrier "barristor" (GB), in which the key is an atomically sharp interface between graphene and hydrogenated silicon. Large modulation on the device current (on/off ratio of 10(5)) is achieved by adjusting the gate voltage to control the graphene-silicon Schottky barrier. The absence of Fermi-level pinning at the interface allows the barrier's height to be tuned to 0.2 electron volt by adjusting graphene's work function, which results in large shifts of diode threshold voltages. Fabricating GBs on respective 150-mm wafers and combining complementary p- and n-type GBs, we demonstrate inverter and half-adder logic circuits.

Graphene-polymer hybrid nanostructure-based bioenergy storage device for real-time control of biological motor activity.

We report a graphene-polymer hybrid nanostructure-based bioenergy storage device to turn on and off biomotor activity in real-time. In this strategy, graphene was functionalized with amine groups and utilized as a transparent electrode supporting the motility of biomotors. Conducting polymer patterns doped with adenosine triphosphate (ATP) were fabricated on the graphene and utilized for the fast release of ATP by electrical stimuli through the graphene. The controlled release of biomotor fuel, ATP, allowed us to control the actin filament transportation propelled by the biomotor in real-time. This strategy should enable the integrated nanodevices for the real-time control of biological motors, which can be a significant stepping stone toward hybrid nanomechanical systems based on motor proteins.

Scanning noise microscopy on graphene devices.

We developed a scanning noise microscopy (SNM) method and demonstrated the nanoscale noise analysis of a graphene strip-based device. Here, a Pt tip made a direct contact on the surface of a nanodevice to measure the current noise spectrum through it. Then, the measured noise spectrum was analyzed by an empirical model to extract the noise characteristics only from the device channel. As a proof of concept, we demonstrated the scaling behavior analysis of the noise in graphene strips. Furthermore, we performed the nanoscale noise mapping on a graphene channel, allowing us to study the effect of structural defects on the noise of the graphene channel. The SNM method is a powerful tool for nanoscale noise analysis and should play a significant role in basic research on nanoscale devices.

Metallic nanowire-graphene hybrid nanostructures for highly flexible field emission devices.

We report a simple but efficient method to prepare metallic nanowire-graphene (MN-G) hybrid nanostructures at a low temperature and show its application to the fabrication of flexible field emission devices. In this method, a graphene layer was transferred onto an anodic alumina oxide template, and vertically aligned Au nanowires were grown on the graphene surface via electrodeposition method. As a proof of concept, we demonstrated the fabrication of flexible field emission devices, where the MN-G hybrid nanostructures and another graphene layer on PDMS substrates were utilized as a cathode and an anode for highly flexible devices, respectively. Our field emission device exhibited stable and high field emission currents even when bent down to the radius of curvature of 25 mm. This MN-G hybrid nanostructure should prove tremendous flexibility for various applications such as bio-chemical sensors, field emission devices, pressure sensors and battery electrodes.

A fast, high-endurance and scalable non-volatile memory device made from asymmetric Ta2O(5-x)/TaO(2-x) bilayer structures.

Numerous candidates attempting to replace Si-based flash memory have failed for a variety of reasons over the years. Oxide-based resistance memory and the related memristor have succeeded in surpassing the specifications for a number of device requirements. However, a material or device structure that satisfies high-density, switching-speed, endurance, retention and most importantly power-consumption criteria has yet to be announced. In this work we demonstrate a TaO(x)-based asymmetric passive switching device with which we were able to localize resistance switching and satisfy all aforementioned requirements. In particular, the reduction of switching current drastically reduces power consumption and results in extreme cycling endurances of over 10(12). Along with the 10 ns switching times, this allows for possible applications to the working-memory space as well. Furthermore, by combining two such devices each with an intrinsic Schottky barrier we eliminate any need for a discrete transistor or diode in solving issues of stray leakage current paths in high-density crossbar arrays.

Passivation of metal surface states: microscopic origin for uniform monolayer graphene by low temperature chemical vapor deposition.

Scanning tunneling microscopy (STM) and density functional theory (DFT) calculations were used to investigate the surface morphology and electronic structure of graphene synthesized on Cu by low temperature chemical vapor deposition (CVD). Periodic line patterns originating from the arrangements of carbon atoms on the Cu surface passivate the interaction between metal substrate and graphene, resulting in flawless inherent graphene band structure in pristine graphene/Cu. The effective elimination of metal surface states by the passivation is expected to contribute to the growth of monolayer graphene on Cu, which yields highly enhanced uniformity on the wafer scale, making progress toward the commercial application of graphene.

Electrical manipulation of nanofilaments in transition-metal oxides for resistance-based memory.

The fabrication of controlled nanostructures such as quantum dots, nanotubes, nanowires, and nanopillars has progressed rapidly over the past 10 years. However, both bottom-up and top-down methods to integrate the nanostructures are met with several challenges. For practical applications with the high level of the integration, an approach that can fabricate the required structures locally is desirable. In addition, the electrical signal to construct and control the nanostructures can provide significant advantages toward the stability and ordering. Through experiments on the negative resistance switching phenomenon in Pt-NiO-Pt structures, we have fabricated nanofilament channels that can be electrically connected or disconnected. Various analyses indicate that the nanofilaments are made of nickel and are formed at the grain boundaries. The scaling behaviors of the nickel nanofilaments were closely examined, with respect to the switching time, power, and resistance. In particular, the 100 nm x 100 nm cell was switchable on the nanosecond scale, making them ideal for the basis for high-speed, high-density, nonvolatile memory applications.