FGSC: Fuzzy Guided Scale Choice SSD Model for Edge AI Design on Real-Time Vehicle Detection and Class Counting.

The aim of this paper is to distinguish the vehicle detection and count the class number in each classification from the inputs. We proposed the use of Fuzzy Guided Scale Choice (FGSC)-based SSD deep neural network architecture for vehicle detection and class counting with parameter optimization. The 'FGSC' blocks are integrated into the convolutional layers of the model, which emphasize essential features while ignoring less important ones that are not significant for the operation. We created the passing detection lines and class counting windows and connected them with the proposed FGSC-SSD deep neural network model. The 'FGSC' blocks in the convolution layer emphasize essential features and find out unnecessary features by using the scale choice method at the training stage and eliminate that significant speedup of the model. In addition, FGSC blocks avoided many unusable parameters in the saturation interval and improved the performance efficiency. In addition, the Fuzzy Sigmoid Function (FSF) increases the activation interval through fuzzy logic. While performing operations, the FGSC-SSD model reduces the computational complexity of convolutional layers and their parameters. As a result, the model tested Frames Per Second (FPS) on edge artificial intelligence (AI) and reached a real-time processing speed of 38.4 and an accuracy rate of more than 94%. Therefore, this work might be considered an improvement to the traffic monitoring approach by using edge AI applications.

A 0.3 V PNN Based 10T SRAM with Pulse Control Based Read-Assist and Write Data-Aware Schemes for Low Power Applications.

An innovative and stable PNN based 10-transistor (10T) static random-access memory (SRAM) architecture has been designed for low-power bit-cell operation and sub-threshold voltage applications. The proposed design belongs to the following features: (a) pulse control based read-assist circuit offers a dynamic read decoupling approach for eliminating the read interference; (b) we have utilized the write data-aware techniques to cut off the pull-down path; and (c) additional write current has enhanced the write capability during the operation. The proposed design not only solves the half-selected problems and increases the read static noise margin (RSNM) but also provides low leakage power performance. The designed architecture of 1-Kb SRAM macros (32 rows × 32 columns) has been implemented based on the TSMC-40 nm GP CMOS process technology. At 300 mV supply voltage and 10 MHz operating frequency, the read and write power consumption is 4.15 µW and 3.82 µW, while the average energy consumption is only 0.39 pJ.