Algorithm and VLSI Architecture Design of Low-Power SPIHT Decoder for mHealth Applications.

A real-time cost and power-efficient (CPE) set partitioning in hierarchical trees (SPIHT) decoder design with low hardware complexity and low-power dissipation is introduced in one-dimension (1-D) wavelet-based quality-assured electrocardiograph (ECG) compression systems for mobile health (mHealth) applications. However, current SPIHT coding architectures are designed for image/video processing. These architectures require a large amount of memory as well as complicated sorting algorithms, which both require time-consuming tasks and are unsuitable for mobile ECG applications. Based on our previously modified SPIHT coding work, which used flags and check bits to reduce memory requirements and coding complexity by merging three search processes into one step. Therefore, to achieve the real-time design goal for mobile ECG applications, in this paper, we first introduce a hardware-oriented SPIHT decoding algorithm that is suitable for decoding the previously presented SPIHT coding work. Accordingly, an appropriate low-power hardware architecture is developed to implement a real-time high-performance and low-cost SPIHT VLSI design for our proposed decoder algorithm, which is appropriate for mobile ECG applications. Using the distinct ECG signals in the MIT-BIH arrhythmia database (sampling rate of 360 Hz), the final simulation and VLSI implementation results reveal that the proposed CPE SPIHT decoder design outperforms the state-of-the-art designs in terms of the average decoding time, the decoding quality, the VLSI speed, and the power consumption. Most importantly, the design can be exploited to a 1-D 1024 × 1 wavelet-based quality-assured ECG data compression system.

A Speed- and Power-Efficient SPIHT Design for Wearable Quality-On-Demand ECG Applications.

In this paper, a speed and power-efficient set partitioning in hierarchical trees (SPIHT) design is introduced for one-dimensional (1-D) wavelet-based electrocardiography (ECG) compression systems with quality guarantee. To achieve real-time and low-power design objectives toward wearable quality-on-demand (QoD) ECG applications, we first propose a coding-time- and computation-efficient SPIHT algorithm using various types of coding status register files to overcome the disadvantages of low coding speeds and complicated hardware architectures characterizing prior SPIHT algorithms resulting from the necessity of dynamic computation and arrangement in the sorting and refinement processing phase. Second, a highly pipelined and power-efficient very large scale integration (VLSI) architecture is developed to implement a high-performance and low-power SPIHT design based on the proposed algorithm. The final simulation results demonstrate that our proposed algorithm can speed up the average coding time 1.52 to 2.74 times compared to prior work with an identical compression ratio for an 11-level $1024\times 1\,1-{\rm{D}}$ discrete wavelet transform at diverse target percentage root-mean-square differences (PRDT) on various MIT-BIH arrhythmia datasets. Applied to wearable wavelet-based QoD ECG applications, our proposed VLSI architecture attains a working frequency of 740 MHz and consumes an average of $\text{23}\ \mu {\text{W}}$ of power with Taiwan Semiconductor Manufacturing Company 90-nm CMOS technology, which shows the effectiveness of speed and power over the state-of-the-art designs.