Power-Efficient LFP-Adaptive Dynamic Zoom-and-Track Incremental ΔΣ Front-End for Dual-Band Subcortical Recordings.

We report a power-efficient analog front-end integrated circuit (IC) for multi-channel, dual-band subcortical recordings. In order to achieve high-resolution multi-channel recordings with low power consumption, we implemented an incremental ΔΣ ADC (IADC) with a dynamic zoom-and-track scheme. This scheme continuously tracks local field potential (LFP) and adaptively adjusts the input dynamic range (DR) into a zoomed sub-LFP range to resolve tiny action potentials. Thanks to the reduced DR, the oversampling rate of the IADC can be reduced by 64.3% compared to the conventional approach, leading to significant power reduction. In addition, dual-band recording can be easily attained because the scheme continuously tracks LFPs without additional on-chip hardware. A prototype four-channel front-end IC has been fabricated in 180 nm standard CMOS processes. The IADC achieved 11.3-bit ENOB at 6.8 µW, resulting in the best Walden and SNDR FoMs, 107.9 fJ/c-s and 162.1 dB, respectively, among two different comparison groups: the IADCs reported up to date in the state-of-the-art neural recording front-ends; and the recent brain recording ADCs using similar zooming or tracking techniques to this work. The intrinsic dual-band recording feature reduces the post-processing FPGA resources for subcortical signal band separation by >45.8%. The front-end IC with the zoom-and-track IADC showed an NEF of 5.9 with input-referred noise of 8.2 µVrms, sufficient for subcortical recording. The performance of the whole front-end IC was successfully validated through in vivo animal experiments.

A 3.1-5.2GHz, Energy-Efficient Single Antenna, Cancellation-Free, Bitwise Time-Division Duplex Transceiver for High Channel Count Optogenetic Neural Interface.

We report an energy-efficient, cancellation-free, bit-wise time-division duplex (B-TDD) transceiver (TRX) for real-time closed-loop control of high channel count neural interfaces. The proposed B-TDD architecture consists of a duty-cycled ultra-wide band (UWB) transmitter (3.1-5 GHz) and a switching U-NII band (5.2 GHz) receiver. An energy-efficient duplex is realized in a single antenna without power-hungry self-interference cancellation circuits which are prevalently used in the conventional full-duplex, single antenna transceivers. To suppress the interference between up- and down-links and enhance the isolation between the two, we devised a fast-switching scheme in a low noise amplifier and used 5× oversampling with a built-in winner-take-all voting in the receiver. The B-TDD transceiver was fabricated in 65 nm CMOS RF process, achieving low energy consumption of 0.32 nJ/b at 10 Mbps in the receiver and 9.7 pJ/b at 200 Mbps in the transmitter, respectively. For validation, the B-TDD TRX has been integrated with a µLED optoelectrode and a custom analog frontend integrated circuit in a prototype wireless bidirectional neural interface system. Successful in-vivo operation for simultaneously recording broadband neural signals and optical stimulation was demonstrated in a transgenic rodent.

A Miniaturized 256-Channel Neural Recording Interface With Area-Efficient Hybrid Integration of Flexible Probes and CMOS Integrated Circuits.

We report a miniaturized, minimally invasive high-density neural recording interface that occupies only a 1.53 mm2 footprint for hybrid integration of a flexible probe and a 256-channel integrated circuit chip. To achieve such a compact form factor, we developed a custom flip-chip bonding technique using anisotropic conductive film and analog circuit-under-pad in a tiny pitch of 75 µm. To enhance signal-to-noise ratios, we applied a reference-replica topology that can provide the matched input impedance for signal and reference paths in low-noise aimpliers (LNAs). The analog front-end (AFE) consists of LNAs, buffers, programmable gain amplifiers, 10b ADCs, a reference generator, a digital controller, and serial-peripheral interfaces (SPIs). The AFE consumes 51.92 µW from 1.2 V and 1.8 V supplies in an area of 0.0161 mm2 per channel, implemented in a 180 nm CMOS process. The AFE shows > 60 dB mid-band CMRR, 6.32 µVrms input-referred noise from 0.5 Hz to 10 kHz, and 48 MΩ input impedance at 1 kHz. The fabricated AFE chip was directly flip-chip bonded with a 256-channel flexible polyimide neural probe and assembled in a tiny head-stage PCB. Full functionalities of the fabricated 256-channel interface were validated in both in vitro and in vivo experiments, demonstrating the presented hybrid neural recording interface is suitable for various neuroscience studies in the quest of large scale, miniaturized recording systems.