CMOS Image Sensor for Broad Spectral Range with >90% Quantum Efficiency.

Even though the recent progress made in complementary metal-oxide-semiconductor (CMOS) image sensors (CIS) has enabled numerous applications affecting our daily lives, the technology still relies on conventional methods such as antireflective coatings and ion-implanted back-surface field to reduce optical and electrical losses resulting in limited device performance. In this work, these methods are replaced with nanostructured surfaces and atomic layer deposited surface passivation. The results show that such surface nanoengineering applied to a commercial backside illuminated CIS significantly extends its spectral range and enhances its photosensitivity as demonstrated by >90% quantum efficiency in the 300-700 nm wavelength range. The surface nanoengineering also reduces the dark current by a factor of three. While the photoresponse uniformity of the sensor is seen to be slightly better, possible scattering from the nanostructures can lead to increased optical crosstalk between the pixels. The results demonstrate the vast potential of surface nanoengineering in improving the performance of CIS for a wide range of applications.

Simulations and Design of a Single-Photon CMOS Imaging Pixel Using Multiple Non-Destructive Signal Sampling.

A single-photon CMOS image sensor (CIS) design based on pinned photodiode (PPD) with multiple charge transfers and sampling is described. In the proposed pixel architecture, the photogenerated signal is sampled non-destructively multiple times and the results are averaged. Each signal measurement is statistically independent and by averaging, the electronic readout noise is reduced to a level where single photons can be distinguished reliably. A pixel design using this method was simulated in TCAD and several layouts were generated for a 180-nm CMOS image sensor process. Using simulations, the noise performance of the pixel was determined as a function of the number of samples, sense node capacitance, sampling rate and transistor characteristics. The strengths and limitations of the proposed design are discussed in detail, including the trade-off between noise performance and readout rate and the impact of charge transfer inefficiency (CTI). The projected performance of our first prototype device indicates that single-photon imaging is within reach and could enable ground-breaking performances in many scientific and industrial imaging applications.

Design and Performance of a Pinned Photodiode CMOS Image Sensor Using Reverse Substrate Bias.

A new pinned photodiode (PPD) CMOS image sensor with reverse biased p-type substrate has been developed and characterized. The sensor uses traditional PPDs with one additional deep implantation step to suppress the parasitic reverse currents, and can be fully depleted. The first prototypes have been manufactured on an 18 µm thick, 1000 Ω·cm epitaxial silicon wafers using 180 nm PPD image sensor process. Both front-side illuminated (FSI) and back-side illuminated (BSI) devices were manufactured in collaboration with Teledyne e2v. The characterization results from a number of arrays of 10 µm and 5.4 µm PPD pixels, with different shape, the size and the depth of the new implant are in good agreement with device simulations. The new pixels could be reverse-biased without parasitic leakage currents well beyond full depletion, and demonstrate nearly identical optical response to the reference non-modified pixels. The observed excessive charge sharing in some pixel variants is shown to not be a limiting factor in operation. This development promises to realize monolithic PPD CIS with large depleted thickness and correspondingly high quantum efficiency at near-infrared and soft X-ray wavelengths.