Thermal Compact Modeling and Resistive Switching Analysis in Titanium Oxide-Based Memristors.

Resistive switching devices based on the Au/Ti/TiO2/Au stack were developed. In addition to standard electrical characterization by means of I-V curves, scanning thermal microscopy was employed to localize the hot spots on the top device surface (linked to conductive nanofilaments, CNFs) and perform in-operando tracking of temperature in such spots. In this way, electrical and thermal responses can be simultaneously recorded and related to each other. In a complementary way, a model for device simulation (based on COMSOL Multiphysics) was implemented in order to link the measured temperature to simulated device temperature maps. The data obtained were employed to calculate the thermal resistance to be used in compact models, such as the Stanford model, for circuit simulation. The thermal resistance extraction technique presented in this work is based on electrical and thermal measurements instead of being indirectly supported by a single fitting of the electrical response (using just I-V curves), as usual. Besides, the set and reset voltages were calculated from the complete I-V curve resistive switching series through different automatic numerical methods to assess the device variability. The series resistance was also obtained from experimental measurements, whose value is also incorporated into a compact model enhanced version.

Spatially-Resolved Thermometry of Filamentary Nanoscale Hot Spots in TiO2 Resistive Random Access Memories to Address Device Variability.

Resistive random access memories (RRAM), based on the formation and rupture of conductive nanoscale filaments, have attracted increased attention for application in neuromorphic and in-memory computing. However, this technology is, in part, limited by its variability, which originates from the stochastic formation and extreme heating of its nanoscale filaments. In this study, we used scanning thermal microscopy (SThM) to assess the effect of filament-induced heat spreading on the surface of metal oxide RRAMs with different device designs. We evaluate the variability of TiO2 RRAM devices with area sizes of 2 × 2 and 5 × 5 µm2. Electrical characterization shows that the variability indicated by the standard deviation of the forming voltage is ∼2 times larger for 5 × 5 µm2 devices than for the 2 × 2 µm2 ones. Further knowledge on the reason for this variability is gained through the SThM thermal maps. These maps show that for 2 × 2 µm2 devices the formation of one filament, i.e., hot spot at the device surface, happens reliably at the same location, while the filament location varies for the 5 × 5 µm2 devices. The thermal information, combined with the electrical, interfacial, and geometric characteristics of the device, provides additional insights into the operation and variability of RRAMs. This work suggests thermal engineering and characterization routes to optimize the efficiency and reliability of these devices.

Nanoscale temperature sensing of electronic devices with calibrated scanning thermal microscopy.

Heat dissipation threatens the performance and lifetime of many electronic devices. As the size of devices shrinks to the nanoscale, we require spatially and thermally resolved thermometry to observe their fine thermal features. Scanning thermal microscopy (SThM) has proven to be a versatile measurement tool for characterizing the temperature at the surface of devices with nanoscale resolution. SThM can obtain qualitative thermal maps of a device using an operating principle based on a heat exchange process between a thermo-sensitive probe and the sample surface. However, the quantification of these thermal features is one of the most challenging parts of this technique. Developing reliable calibration approaches for SThM is therefore an essential aspect to accurately determine the temperature at the surface of a sample or device. In this work, we calibrate a thermo-resistive SThM probe using heater-thermometer metal lines with different widths (50 nm to 750 nm), which mimic variable probe-sample thermal exchange processes. The sensitivity of the SThM probe when scanning the metal lines is also evaluated under different probe and line temperatures. Our results reveal that the calibration factor depends on the probe measuring conditions and on the size of the surface heating features. This approach is validated by mapping the temperature profile of a phase change electronic device. Our analysis provides new insights on how to convert the thermo-resistive SThM probe signal to the scanned device temperature more accurately.

Ferrofluidic thermal switch in a magnetocaloric device.

Thermal switches are advanced heat-management devices that represent a new opportunity to improve the energy efficiency and power density of caloric devices. In this study we have developed a numerical model to analyze the operation and the performance of static thermal switches in caloric refrigeration. The investigation comprises a parametric analysis of a realistic ferrofluidic thermal switch in terms of the maximum temperature span, cooling power, and coefficient of performance. The highest achieved temperature span between the heat source and the heat sink was 1.12 K for a single embodiment, which could be further developed into a regenerative system to increase the temperature span. A sensitivity analysis is conducted to correlate the relationship between the input parameters and the results. We show that thermal switches can be used in caloric devices even when switching ratios are small, which greatly extends the possibilities to implement different types of thermal switches.

Thermal rectification in multilayer phase change material structures for energy storage applications.

Solid-state thermal control devices that present an asymmetric heat flow depending on thermal bias directionality, referred to as thermal diodes, have recently received increased attention for energy management. The use of materials that can change phase is a common approach to design thermal diodes, but typical sizes, moderate rectification ratios, and narrow thermal tunability limit their potential applications. In this work, we propose a multilayer thermal diode made of a combination of phase change and invariant materials. This device presents state-of-the-art thermal rectification ratios up to 136% for a temperature range between 300 K and 500 K. Importantly, this design allows to switch between distinct rectification states that can be modulated with temperature, achieving an additional degree of thermal control compared with single-rectification-state devices. We analyze the relevance of our thermal diodes for retaining heat more efficiently in thermal storage elements.

Selectivity Map for Molecular Beam Epitaxy of Advanced III-V Quantum Nanowire Networks.

Selective-area growth is a promising technique for enabling of the fabrication of the scalable III-V nanowire networks required to test proposals for Majorana-based quantum computing devices. However, the contours of the growth parameter window resulting in selective growth remain undefined. Herein, we present a set of experimental techniques that unambiguously establish the parameter space window resulting in selective III-V nanowire networks growth by molecular beam epitaxy. Selectivity maps are constructed for both GaAs and InAs compounds based on in situ characterization of growth kinetics on GaAs(001) substrates, where the difference in group III adatom desorption rates between the III-V surface and the amorphous mask area is identified as the primary mechanism governing selectivity. The broad applicability of this method is demonstrated by the successful realization of high-quality InAs and GaAs nanowire networks on GaAs, InP, and InAs substrates of both (001) and (111)B orientations as well as homoepitaxial InSb nanowire networks. Finally, phase coherence in Aharonov-Bohm ring experiments validates the potential of these crystals for nanoelectronics and quantum transport applications. This work should enable faster and better nanoscale crystal engineering over a range of compound semiconductors for improved device performance.