Field-programmable logic devices with optical input-output.

A field-programmable logic device (FPLD) with optical I/O is described. FPLD's with optical I/O can have their functionality specified in the field by means of downloading a control-bit stream and can be used in a wide range of applications, such as optical signal processing, optical image processing, and optical interconnects. Our device implements six state-of-the-art dynamically programmable logic arrays (PLA's) on a 2 mm x 2 mm die. The devices were fabricated through the Lucent Technologies-Advanced Research Projects Agency-Consortium for Optical and Optoelectronic Technologies in Computing (Lucent/ARPA/COOP) workshop by use of 0.5-microm complementary metal-oxide semiconductor-self-electro-optic device technology and were delivered in 1998. All devices are fully functional: The electronic data paths have been verified at 200 MHz, and optical tests are pending. The device has been programmed to implement a two-stage optical switching network with six 4 x 4 crossbar switches, which can realize more than 190 x 10(6) unique programmable input-output permutations. The same device scaled to a 2 cm x 2 cm substrate could support as many as 4000 optical I/O and 1 Tbit/s of optical I/O bandwidth and offer fully programmable digital functionality with approximately 110,000 programmable logic gates. The proposed optoelectronic FPLD is also ideally suited to realizing dense, statically reconfigurable crossbar switches. We describe an attractive application area for such devices: a rearrangeable three-stage optical switch for a wide-area-network backbone, switching 1000 traffic streams at the OC-48 data rate and supporting several terabits of traffic.

Bandwidth optimization of optical data links by use of error-control codes.

A design approach to optimizing the bandwidth of optical data links while simultaneously decreasing the bit-error rate is proposed. Mathematical analysis indicates that bandwidth gains by factors of 10-60 with power gains of as much as 8.9 dB are possible. To achieve these performance levels requires several innovations. First, conventional forward error-correcting codes cannot be used because of their excessive hardware cost. A reasonably powerful multidimensional parity-based error-control code is proposed and analyzed. These codes offer excellent error detection and moderate error-correction capabilities. Most importantly, they can operate at the fast clock rates that are required. Second, a hybrid automatic-repeat-request protocol is exploited to correct complex error patterns. In thermal-noise-limited systems this unique combination allows the optical clock rate to be increased significantly, thereby resulting in large bandwidth increases. The proposed design approach can be used in optical data links in which propagation delays are moderate and is applicable to fibers that exploit wavelength-division multiplexing or time-division multiplexing, one-dimensional parallel-fiber ribbons, and two-dimensional optical data links that use free space or guided waves. Several design examples are illustrated.

Testbed for a scalable terabit optical local area network.

The design of a fiber-optic local area network (LAN) demonstration system is described. A complete LAN system would consist of an array of 16 personal computers (PC's), where each PC has a network interface card (NIC) with a parallel fiber-optic datalink to a centralized optoelectronic switch core. The centralized core switches the data generated by 16 NIC's, up to 128 Gbit/s of bandwidth. The demonstrator is designed to scale to terabits of bandwidth by use of an emerging optoelectronic technology, i.e., integrated complementary metal-oxide semiconductor (CMOS) substrates with vertical-cavity surface-emitting laser (VCSEL) and photodetector optical input and output. A subset of the complete system was constructed and is operational. A prototype NIC card, with Motorola Optobus VCSEL transceivers for the optical datalinks, was constructed and is described. A prototype high-speed bipolar switch core, with statically configurable electrical positive-emitter coupled-logic 16 x 16 crossbar switches, CMOS field-programmable gate arrays, and Motorola Optobus transceivers, was constructed and is described. We successfully demonstrated the transmission of high-speed packetized data from one NIC card, through 10 m of parallel fiber ribbon and the centralized switch core, and back to the NIC. We summarize our experiences on the design and testing of our first demonstration system and our development toward a terabit switch core.

Field-programmable smart-pixel arrays: design, VLSI implementation, and applications.

A smart-pixel array is a two-dimensional array of optoelectronic devices that combine optical inputs and outputs with electronic processing circuitry. A field-programmable smart-pixel array (FP-SPA) is a smart-pixel array capable of having its electronic functionality dynamically programmed in the field. Such devices could be used in a diverse range of applications, including optical switching, optical digital signal processing, and optical image processing. We describe the design, VLSI implementation, and applications of a first-generation FP-SPA implemented with the 0.8-microm complementary metal-oxide semiconductor-self-electro-optic effect device technology made available through the Lucent Technologies-Advanced Research Projects Agency Cooperative (Lucent/ARPA/COOP) program. We report spice simulations and experimental results of two sample applications: In the first application, we configure this FP-SPA as an array of free-space optical binary switches that can be used in optical multistage networks. In the second, we configure the device as an optoelectronic transceiver for a dynamically reconfigurable free-space intelligent optical backplane called the hyperplane. We also describe the testing setup and the electrical and the optical tests that demonstrate the correct functionality of the fabricated device. Such devices have the potential to reduce significantly the need for custom design and fabrication of application-specific optoelectronic devices in the same manner that field-programmable gate arrays have largely eliminated the need for custom design and fabrication of application-specific gate arrays, except in the most demanding applications.

Terabit optical local area networks for multiprocessing systems.

The design of a scalable optical local area network formultiprocessing systems is described. Each workstation has aparallel-fiber-ribbon optical link to a centralized complementarymetal-oxide silicon (CMOS) switch core, implemented on a singlecompact printed circuit board (PCB). When the Motorola Optobusfiber technology is used, each workstation has a data bandwidth of 6.4Gbits/s to the core. A centralized switch core interconnecting 32workstations supports a 204-Gbit/s aggregate data bandwidth. Theswitch core is based on a conventional broadcast-and-selectarchitecture, implemented with parallel CMOS integrated circuits(IC's). The switch core scales well; by incorporation of theCMOS optoelectronic IC's with optical input-output, the electricalcore can be reduced to a single-chip optoelectronic IC with terabitcapacities. A prototype of an optoelectronic switch core has been fabricated and is described. The appeal of the architectureincludes its reliance on commercially available parallel-fibertechnology, its reliance on the well-developed markets of local areanetworks and networks of workstations, and its smooth scalability from the electrical to optical domains as technology matures.

Reconfigurable intelligent optical backplane for parallel computing and communications.

A reconfigurable intelligent optical backplane architecture for parallel computing and communications is described. The backplane consists of a large number of reconfigurable optical channels organized in a ring with relatively simple point-to-point optical interconnections between neighboring smart-pixel arrays. The intelligent backplane can implement (l) dynamically reconfigurable connections between any printed circuit boards, (2) dynamic embeddings of classical interconnection networks such as buses, rings, multidimensional meshes, hypercubes, shuffles, and crossbars, (3) multipoint switching, (4) sorting, (5) parallel-prefix operations, (6) pattern-matching operations, (7) snoopy caches and intelligent memory systems, and (8) media-access control functions. The smart-pixel arrays can be enhanced to include more complex functions, such as queuing and routing, as the technologies mature. Descriptions of the architecture and the smart-pixel arrays and discussions of the system cost, availability, and performance are included.