Single-Electron Occupation in Quantum Dot Arrays at Selectable Plunger Gate Voltage.

The small footprint of semiconductor qubits is favorable for scalable quantum computing. However, their size also makes them sensitive to their local environment and variations in the gate structure. Currently, each device requires tailored gate voltages to confine a single charge per quantum dot, clearly challenging scalability. Here, we tune these gate voltages and equalize them solely through the temporary application of stress voltages. In a double quantum dot, we reach a stable (1,1) charge state at identical and predetermined plunger gate voltage and for various interdot couplings. Applying our findings, we tune a 2 × 2 quadruple quantum dot such that the (1,1,1,1) charge state is reached when all plunger gates are set to 1 V. The ability to define required gate voltages may relax requirements on control electronics and operations for spin qubit devices, providing means to advance quantum hardware.

Probing the Jaynes-Cummings Ladder with Spin Circuit Quantum Electrodynamics.

We report observations of transitions between excited states in the Jaynes-Cummings ladder of circuit quantum electrodynamics with electron spins (spin circuit QED). We show that unexplained features in recent experimental work correspond to such transitions and present an input-output framework that includes these effects. In new experiments, we first reproduce previous observations and then reveal both excited-state transitions and multiphoton transitions by increasing the probe power and using two-tone spectroscopy. This ability to probe the Jaynes-Cummings ladder is enabled by improvements in the coupling-to-decoherence ratio, and shows an increase in the maturity of spin circuit QED as an interesting platform for studying quantum phenomena.

Reducing charge noise in quantum dots by using thin silicon quantum wells.

Charge noise in the host semiconductor degrades the performance of spin-qubits and poses an obstacle to control large quantum processors. However, it is challenging to engineer the heterogeneous material stack of gate-defined quantum dots to improve charge noise systematically. Here, we address the semiconductor-dielectric interface and the buried quantum well of a 28Si/SiGe heterostructure and show the connection between charge noise, measured locally in quantum dots, and global disorder in the host semiconductor, measured with macroscopic Hall bars. In 5 nm thick 28Si quantum wells, we find that improvements in the scattering properties and uniformity of the two-dimensional electron gas over a 100 mm wafer correspond to a significant reduction in charge noise, with a minimum value of 0.29 ± 0.02 µeV/Hz½ at 1 Hz averaged over several quantum dots. We extrapolate the measured charge noise to simulated dephasing times to CZ-gate fidelities that improve nearly one order of magnitude. These results point to a clean and quiet crystalline environment for integrating long-lived and high-fidelity spin qubits into a larger system.

Atomic fluctuations lifting the energy degeneracy in Si/SiGe quantum dots.

Electron spins in Si/SiGe quantum wells suffer from nearly degenerate conduction band valleys, which compete with the spin degree of freedom in the formation of qubits. Despite attempts to enhance the valley energy splitting deterministically, by engineering a sharp interface, valley splitting fluctuations remain a serious problem for qubit uniformity, needed to scale up to large quantum processors. Here, we elucidate and statistically predict the valley splitting by the holistic integration of 3D atomic-level properties, theory and transport. We find that the concentration fluctuations of Si and Ge atoms within the 3D landscape of Si/SiGe interfaces can explain the observed large spread of valley splitting from measurements on many quantum dot devices. Against the prevailing belief, we propose to boost these random alloy composition fluctuations by incorporating Ge atoms in the Si quantum well to statistically enhance valley splitting.

Universal control of a six-qubit quantum processor in silicon.

Future quantum computers capable of solving relevant problems will require a large number of qubits that can be operated reliably1. However, the requirements of having a large qubit count and operating with high fidelity are typically conflicting. Spins in semiconductor quantum dots show long-term promise2,3 but demonstrations so far use between one and four qubits and typically optimize the fidelity of either single- or two-qubit operations, or initialization and readout4-11. Here, we increase the number of qubits and simultaneously achieve respectable fidelities for universal operation, state preparation and measurement. We design, fabricate and operate a six-qubit processor with a focus on careful Hamiltonian engineering, on a high level of abstraction to program the quantum circuits, and on efficient background calibration, all of which are essential to achieve high fidelities on this extended system. State preparation combines initialization by measurement and real-time feedback with quantum-non-demolition measurements. These advances will enable testing of increasingly meaningful quantum protocols and constitute a major stepping stone towards large-scale quantum computers.

Quantum logic with spin qubits crossing the surface code threshold.

High-fidelity control of quantum bits is paramount for the reliable execution of quantum algorithms and for achieving fault tolerance-the ability to correct errors faster than they occur1. The central requirement for fault tolerance is expressed in terms of an error threshold. Whereas the actual threshold depends on many details, a common target is the approximately 1% error threshold of the well-known surface code2,3. Reaching two-qubit gate fidelities above 99% has been a long-standing major goal for semiconductor spin qubits. These qubits are promising for scaling, as they can leverage advanced semiconductor technology4. Here we report a spin-based quantum processor in silicon with single-qubit and two-qubit gate fidelities, all of which are above 99.5%, extracted from gate-set tomography. The average single-qubit gate fidelities remain above 99% when including crosstalk and idling errors on the neighbouring qubit. Using this high-fidelity gate set, we execute the demanding task of calculating molecular ground-state energies using a variational quantum eigensolver algorithm5. Having surpassed the 99% barrier for the two-qubit gate fidelity, semiconductor qubits are well positioned on the path to fault tolerance and to possible applications in the era of noisy intermediate-scale quantum devices.

Quantum-coherent nanoscience.

For the past three decades nanoscience has widely affected many areas in physics, chemistry and engineering, and has led to numerous fundamental discoveries, as well as applications and products. Concurrently, quantum science and technology has developed into a cross-disciplinary research endeavour connecting these same areas and holds burgeoning commercial promise. Although quantum physics dictates the behaviour of nanoscale objects, quantum coherence, which is central to quantum information, communication and sensing, has not played an explicit role in much of nanoscience. This Review describes fundamental principles and practical applications of quantum coherence in nanoscale systems, a research area we call quantum-coherent nanoscience. We structure this Review according to specific degrees of freedom that can be quantum-coherently controlled in a given nanoscale system, such as charge, spin, mechanical motion and photons. We review the current state of the art and focus on outstanding challenges and opportunities unlocked by the merging of nanoscience and coherent quantum operations.

CMOS-based cryogenic control of silicon quantum circuits.

The most promising quantum algorithms require quantum processors that host millions of quantum bits when targeting practical applications1. A key challenge towards large-scale quantum computation is the interconnect complexity. In current solid-state qubit implementations, an important interconnect bottleneck appears between the quantum chip in a dilution refrigerator and the room-temperature electronics. Advanced lithography supports the fabrication of both control electronics and qubits in silicon using technology compatible with complementary metal oxide semiconductors (CMOS)2. When the electronics are designed to operate at cryogenic temperatures, they can ultimately be integrated with the qubits on the same die or package, overcoming the 'wiring bottleneck'3-6. Here we report a cryogenic CMOS control chip operating at 3 kelvin, which outputs tailored microwave bursts to drive silicon quantum bits cooled to 20 millikelvin. We first benchmark the control chip and find an electrical performance consistent with qubit operations of 99.99 per cent fidelity, assuming ideal qubits. Next, we use it to coherently control actual qubits encoded in the spin of single electrons confined in silicon quantum dots7-9 and find that the cryogenic control chip achieves the same fidelity as commercial instruments at room temperature. Furthermore, we demonstrate the capabilities of the control chip by programming a number of benchmarking protocols, as well as the Deutsch-Josza algorithm10, on a two-qubit quantum processor. These results open up the way towards a fully integrated, scalable silicon-based quantum computer.

Electron cascade for distant spin readout.

The spin of a single electron in a semiconductor quantum dot provides a well-controlled and long-lived qubit implementation. The electron charge in turn allows control of the position of individual electrons in a quantum dot array, and enables charge sensors to probe the charge configuration. Here we show that the Coulomb repulsion allows an initial charge transition to induce subsequent charge transitions, inducing a cascade of electron hops, like toppling dominoes. A cascade can transmit information along a quantum dot array over a distance that extends by far the effect of the direct Coulomb repulsion. We demonstrate that a cascade of electrons can be combined with Pauli spin blockade to read out distant spins and show results with potential for high fidelity using a remote charge sensor in a quadruple quantum dot device. We implement and analyse several operating modes for cascades and analyse their scaling behaviour. We also discuss the application of cascade-based spin readout to densely-packed two-dimensional quantum dot arrays with charge sensors placed at the periphery. The high connectivity of such arrays greatly improves the capabilities of quantum dot systems for quantum computation and simulation.

Author Correction: Rapid gate-based spin read-out in silicon using an on-chip resonator.

An amendment to this paper has been published and can be accessed via a link at the top of the paper.

Rapid gate-based spin read-out in silicon using an on-chip resonator.

Silicon spin qubits are one of the leading platforms for quantum computation1,2. As with any qubit implementation, a crucial requirement is the ability to measure individual quantum states rapidly and with high fidelity. Since the signal from a single electron spin is minute, the different spin states are converted to different charge states3,4. Charge detection, so far, has mostly relied on external electrometers5-7, which hinders scaling to two-dimensional spin qubit arrays2,8,9. Alternatively, gate-based dispersive read-out based on off-chip lumped element resonators has been demonstrated10-13, but integration times of 0.2-2 ms were required to achieve single-shot read-out14-16. Here, we connect an on-chip superconducting resonant circuit to two of the gates that confine electrons in a double quantum dot. Measurement of the power transmitted through a feedline coupled to the resonator probes the charge susceptibility, distinguishing whether or not an electron can oscillate between the dots in response to the probe power. With this approach, we achieve a signal-to-noise ratio of about six within an integration time of only 1 µs. Using Pauli's exclusion principle for spin-to-charge conversion, we demonstrate single-shot read-out of a two-electron spin state with an average fidelity of >98% in 6 µs. This result may form the basis of frequency-multiplexed read-out in dense spin qubit systems without external electrometers, therefore simplifying the system architecture.

A crossbar network for silicon quantum dot qubits.

The spin states of single electrons in gate-defined quantum dots satisfy crucial requirements for a practical quantum computer. These include extremely long coherence times, high-fidelity quantum operation, and the ability to shuttle electrons as a mechanism for on-chip flying qubits. To increase the number of qubits to the thousands or millions of qubits needed for practical quantum information, we present an architecture based on shared control and a scalable number of lines. Crucially, the control lines define the qubit grid, such that no local components are required. Our design enables qubit coupling beyond nearest neighbors, providing prospects for nonplanar quantum error correction protocols. Fabrication is based on a three-layer design to define qubit and tunnel barrier gates. We show that a double stripline on top of the structure can drive high-fidelity single-qubit rotations. Self-aligned inhomogeneous magnetic fields induced by direct currents through superconducting gates enable qubit addressability and readout. Qubit coupling is based on the exchange interaction, and we show that parallel two-qubit gates can be performed at the detuning-noise insensitive point. While the architecture requires a high level of uniformity in the materials and critical dimensions to enable shared control, it stands out for its simplicity and provides prospects for large-scale quantum computation in the near future.

Mesoscopic Elastic Distortions in GaAs Quantum Dot Heterostructures.

Quantum devices formed in high-electron-mobility semiconductor heterostructures provide a route through which quantum mechanical effects can be exploited on length scales accessible to lithography and integrated electronics. The electrostatic definition of quantum dots in semiconductor heterostructure devices intrinsically involves the lithographic fabrication of intricate patterns of metallic electrodes. The formation of metal/semiconductor interfaces, growth processes associated with polycrystalline metallic layers, and differential thermal expansion produce elastic distortion in the active areas of quantum devices. Understanding and controlling these distortions present a significant challenge in quantum device development. We report synchrotron X-ray nanodiffraction measurements combined with dynamical X-ray diffraction modeling that reveal lattice tilts with a depth-averaged value up to 0.04° and strain on the order of 10-4 in the two-dimensional electron gas (2DEG) in a GaAs/AlGaAs heterostructure. Elastic distortions in GaAs/AlGaAs heterostructures modify the potential energy landscape in the 2DEG due to the generation of a deformation potential and an electric field through the piezoelectric effect. The stress induced by metal electrodes directly impacts the ability to control the positions of the potential minima where quantum dots form and the coupling between neighboring quantum dots.

Gate fidelity and coherence of an electron spin in an Si/SiGe quantum dot with micromagnet.

The gate fidelity and the coherence time of a quantum bit (qubit) are important benchmarks for quantum computation. We construct a qubit using a single electron spin in an Si/SiGe quantum dot and control it electrically via an artificial spin-orbit field from a micromagnet. We measure an average single-qubit gate fidelity of ∼99% using randomized benchmarking, which is consistent with dephasing from the slowly evolving nuclear spins in the substrate. The coherence time measured using dynamical decoupling extends up to ∼400 µs for 128 decoupling pulses, with no sign of saturation. We find evidence that the coherence time is limited by noise in the 10-kHz to 1-MHz range, possibly because charge noise affects the spin via the micromagnet gradient. This work shows that an electron spin in an Si/SiGe quantum dot is a good candidate for quantum information processing as well as for a quantum memory, even without isotopic purification.

Quantum interference in an interfacial superconductor.

The two-dimensional superconductor that forms at the interface between the complex oxides lanthanum aluminate (LAO) and strontium titanate (STO) has several intriguing properties that set it apart from conventional superconductors. Most notably, an electric field can be used to tune its critical temperature (Tc; ref. 7), revealing a dome-shaped phase diagram reminiscent of high-Tc superconductors. So far, experiments with oxide interfaces have measured quantities that probe only the magnitude of the superconducting order parameter and are not sensitive to its phase. Here, we perform phase-sensitive measurements by realizing the first superconducting quantum interference devices (SQUIDs) at the LAO/STO interface. Furthermore, we develop a new paradigm for the creation of superconducting circuit elements, where local gates enable the in situ creation and control of Josephson junctions. These gate-defined SQUIDs are unique in that the entire device is made from a single superconductor with purely electrostatic interfaces between the superconducting reservoir and the weak link. We complement our experiments with numerical simulations and show that the low superfluid density of this interfacial superconductor results in a large, gate-controllable kinetic inductance of the SQUID. Our observation of robust quantum interference opens up a new pathway to understanding the nature of superconductivity at oxide interfaces.

Nanoscale electrostatic control of oxide interfaces.

We develop a robust and versatile platform to define nanostructures at oxide interfaces via patterned top gates. Using LaAlO3/SrTiO3 as a model system, we demonstrate controllable electrostatic confinement of electrons to nanoscale regions in the conducting interface. The excellent gate response, ultralow leakage currents, and long-term stability of these gates allow us to perform a variety of studies in different device geometries from room temperature down to 50 mK. Using a split-gate device we demonstrate the formation of a narrow conducting channel whose width can be controllably reduced via the application of appropriate gate voltages. We also show that a single narrow gate can be used to induce locally a superconducting to insulating transition. Furthermore, in the superconducting regime we see indications of a gate-voltage controlled Josephson effect.

Quantum dots at room temperature carved out from few-layer graphene.

We present graphene quantum dots endowed with addition energies as large as 1.6 eV, fabricated by the controlled rupture of a graphene sheet subjected to a large electron current in air. The size of the quantum dot islands is estimated to be in the 1 nm range. The large addition energies allow for Coulomb blockade at room temperature, with possible application to single-electron devices.

Lattice expansion in seamless bilayer graphene constrictions at high bias.

Our understanding of sp(2) carbon nanostructures is still emerging and is important for the development of high performance all carbon devices. For example, in terms of the structural behavior of graphene or bilayer graphene at high bias, little to nothing is known. To this end, we investigated bilayer graphene constrictions with closed edges (seamless) at high bias using in situ atomic resolution transmission electron microscopy. We directly observe a highly localized anomalously large lattice expansion inside the constriction. Both the current density and lattice expansion increase as the bilayer graphene constriction narrows. As the constriction width decreases below 10 nm, shortly before failure, the current density rises to 4 × 10(9) A cm(-2) and the constriction exhibits a lattice expansion with a uniaxial component showing an expansion approaching 5% and an isotropic component showing an expansion exceeding 1%. The origin of the lattice expansion is hard to fully ascribe to thermal expansion. Impact ionization is a process in which charge carriers transfer from bonding states to antibonding states, thus weakening bonds. The altered character of C-C bonds by impact ionization could explain the anomalously large lattice expansion we observe in seamless bilayer graphene constrictions. Moreover, impact ionization might also contribute to the observed anisotropy in the lattice expansion, although strain is probably the predominant factor.

Gate-defined confinement in bilayer graphene-hexagonal boron nitride hybrid devices.

We report on the fabrication and measurement of nanoscale devices that permit electrostatic confinement in bilayer graphene on a substrate. The graphene bilayer is sandwiched between hexagonal boron nitride bottom and top gate dielectrics. Top gates are patterned such that constrictions and islands can be electrostatically induced. The high quality of the devices becomes apparent from the smooth pinch-off characteristics of the constrictions at low temperature with features indicative of conductance quantization. The islands exhibit clear Coulomb blockade and single-electron transport.