Atomic layer deposition of aluminum oxide films for carbon nanotube network transistor passivation.

Ultra-thin (2-5 nm thick) aluminum oxide layers were grown on non-functionalized individual single walled carbon nanotubes (SWCNT) and their bundles by atomic layer deposition (ALD) technique in order to investigate the mechanism of the coating process. Transmission electron microscopy (TEM) was used to examine the uniformity and conformality of the coatings grown at different temperatures (80 degrees C or 220 degrees C) and with different precursors for oxidation (water and ozone). We found that bundles of SWCNTs were coated continuously, but at the same time, bare individual nanotubes remained uncoated. The successful coating of bundles was explained by the formation of interstitial pores between the individual SWCNTs constituting the bundle, where the precursor molecules can adhere, initiating the layer growth. Thicker alumina layers (20-35 nm thick) were used for the coating of bottom-gated SWCNT-network based field effect transistors (FETs). ALD layers, grown at different conditions, were found to influence the performance of the SWCNT-network FETs: low temperature ALD layers caused the ambipolarity of the channel and pronounced n-type conduction, whereas high temperature ALD processes resulted in hysteresis suppression in the transfer characteristics of the SWCNT transistors and preserved p-type conduction. Fixed charges in the ALD layer have been considered as the main factor influencing the conduction change of the SWCNT network based transistors.

Carbon nanotube thin film transistors based on aerosol methods.

We demonstrate a fabrication method for high-performance field-effect transistors (FETs) based on dry-processed random single-walled carbon nanotube networks (CNTNs) deposited at room temperature. This method is an advantageous alternative to solution-processed and direct CVD grown CNTN FETs, which allows using various substrate materials, including heat-intolerant plastic substrates, and enables an efficient, density-controlled, scalable deposition of as-produced single-walled CNTNs on the substrate directly from the aerosol (floating catalyst) synthesis reactor. Two types of thin film transistor (TFT) structures were fabricated to evaluate the FET performance of dry-processed CNTNs: bottom-gate transistors on Si/SiO2 substrates and top-gate transistors on polymer substrates. Devices exhibited on/off ratios up to 10(5) and field-effect mobilities up to 4 cm(2) V(-1) s(-1). The suppression of hysteresis in the bottom-gate device transfer characteristics by means of thermal treatment in vacuum and passivation by an atomic layer deposited Al(2)O(3) film was investigated. A 32 nm thick Al(2)O(3) layer was found to be able to eliminate the hysteresis.