Implementation of field-programmable Gate array-based clock synchronization in the fiber channel communication system.

A sub-nanosecond clock synchronization scheme based on the field programmable gate array (FPGA) is proposed for the Fiber Channel (FC) communication system in this paper. The counter value of the slave node is synchronized to that of the master node through the embedded IEEE 1588 protocol over the communication link. In order to ensure the counter clocks have the same frequency in both nodes, which is recovered from the FC communication link, the clock phase difference is measured by the digital dual mixer time difference technique and the data recovery technique in the Gigabyte Transceiver, and then it is compensated by the mixed-mode clock manager in FPGAs. The proposed clock synchronization approach is evaluated with an FC communication system that has a serial rate of 12.5 Gbps, and the reported experimental results show that the proposed clock synchronization module can achieve a time difference lower than 1 ns.

Time-interleaved system mismatch estimation based on correlation function and particle swarm optimization algorithm.

The time-interleaved analog-to-digital converters (TIADCs) technique is an efficient solution to improve the sampling rate of the acquisition system with low-speed ADCs. However, channel mismatches such as gain mismatch, time skew mismatch, and offset mismatch may seriously degrade the performance of TIADC. Furthermore, for high-speed signal acquisition, the gain and time skew mismatches would vary with the signal frequency, and the traditional fixed model does not work any longer. In this paper, a series of sinusoidal signals are adopted to estimate the variable mismatches. First, an autocorrelation-based approach is presented to estimate the gain mismatch. The information about the gain mismatch is extracted from the autocorrelation function of sub-ADC output samples. Then, the time skew mismatch is estimated by utilizing the particle swarm optimization algorithm. The reported simulation results show that the mismatches can be accurately estimated. Finally, a commercial 12.5 GSPS four-channel TIADC system is utilized to verify the performance of the proposed method. The spurious free dynamic range of the system can be improved by about 20 dB, and the effectiveness of the proposed estimation method is demonstrated.

Statistical neural network (SNN) for predicting signal-to-noise ratio (SNR) from static parameters and its validation in 16-bit, 125-MSPS analog-to-digital converters (ADCs).

In the analog-to-digital converter (ADC) test process, the static and dynamic performance parameters are the most important, and the tests for these parameters account for the bulk of the ADC test cost. These two types of parameters follow certain relationships, which are incorporated into the ADC test to reduce the cost. In this paper, we focus on the signal-to-noise ratio (SNR), a key indicator of the dynamic performances of ADCs. A statistical neural network (SNN) with two hidden layers was constructed to predict the SNR from the feature variables, which were extracted from the static parameters. A 16-bit, 125-MSPS ADC was used to evaluate the proposed prediction model. Compared to the measured SNR obtained by traditional fast Fourier transform based test methods, the predicted value had a mean average error of only 0.75 dB. In addition, the Shapley additive explanations interpreter was adopted to analyze the feature dependences of the SNN model, and the results demonstrated that the deterioration of the integral nonlinearity-curve-related features could significantly decrease the SNR, which is consistent with previous research results. The reported results demonstrated that, at the cost of a slight loss of accuracy, the proposed SNN can significantly reduce the test complexity, avoid dynamic parameter measurements, and reduce the total test time by about 4%.

Multiband sparse signal reconstruction through direct one-bit sampling.

Compressive sensing (CS) aims at decreasing sampling rate to reduce the needed number of samples. On the other hand, the one-bit CS is proposed to reduce the quantization bit. In this paper, we proposed a one-bit CS system aiming at acquiring the multiband sparse signal which is a very popular signal model in wireless communication, especially in cognitive radio. This proposed system, called direct one-bit sampler (DOS), is simple in hardware implementation, and it consists of only a comparator working at Nyquist rate. In the stage of signal reconstruction, it can be equivalent to a special multicoset sampler which is a popular scheme in CS. Moreover, we propose an enhanced binary iterative hard thresholding (BIHT), a popular one-bit recovery algorithm, to deal with the multiple measurement vectors in the one-bit CS framework. Both the theoretical model and experimental results demonstrate that the proposed DOS, with the help of the enhanced BIHT, can not only accurately recover the positions of active subbands of the multiband sparse signal but also roughly estimate the power of each active subband.

GHz sampling hardware implementation with sub-Nyquist coprime sampling rates.

A sub-Nyquist coprime sampling system for sparse signals is implemented in this article. The proposed system is composed of coprime sampling hardware and a multicoset signal reconstruction algorithm. A pair of uniform samplers is utilized in the hardware to sample a wideband spare analog signal with an uncertain difference in start times. A time difference acquisition module embedded into a field-programmable gate array and a pulse-expanding circuit are then used to measure the difference in start times. Owing to the different frequencies of the two samplers, the coprime sample sets obtained are nonuniform. Before they are used as input to the multicoset signal reconstruction algorithm, these coprime sample sets need to be regrouped into multicoset sample sets according to the sample pattern. The results of experiments indicate that the signals can be reconstructed at an equivalent rate of the order of gigahertz from sub-Nyquist samples acquired by the designed coprime acquisition system.

Sequential time interleaved random equivalent sampling for repetitive signal.

Compressed sensing (CS) based sampling techniques exhibit many advantages over other existing approaches for sparse signal spectrum sensing; they are also incorporated into non-uniform sampling signal reconstruction to improve the efficiency, such as random equivalent sampling (RES). However, in CS based RES, only one sample of each acquisition is considered in the signal reconstruction stage, and it will result in more acquisition runs and longer sampling time. In this paper, a sampling sequence is taken in each RES acquisition run, and the corresponding block measurement matrix is constructed using a Whittaker-Shannon interpolation formula. All the block matrices are combined into an equivalent measurement matrix with respect to all sampling sequences. We implemented the proposed approach with a multi-cores analog-to-digital converter (ADC), whose ADC cores are time interleaved. A prototype realization of this proposed CS based sequential random equivalent sampling method has been developed. It is able to capture an analog waveform at an equivalent sampling rate of 40 GHz while sampled at 1 GHz physically. Experiments indicate that, for a sparse signal, the proposed CS based sequential random equivalent sampling exhibits high efficiency.