Detachable interface toward a low-loss reflow-compatible fiber coupling for co-packaged optics (CPO).

High-density reflow-compatible fiber I/O is one of the challenges for co-packaged optics (CPO). This paper developed a detachable coupling interface based on expanded beam edge coupling, which can be applied for optical coupling between lasers, PICs, and fibers, seamlessly supporting many channels with high efficiency. It comprises a removable fiber connector and a permanent chip/device connector, in which microlens/lens arrays are used for waveguide mode expansion and MT-like connectors are used for position registration. An effective alignment scheme based on beam detection was developed and implemented in an assembly station for building the removable fiber connectors, while the permanent chip/device connector was assembled by active alignment to a pre-made fiber connector mated with a registration connector. Promising results were obtained from the proof-of-concept demonstrations of the coupling from SiP PIC and III/V lasers to fibers using the off-the-shelf lenses and modified MT registration connectors. In both cases, less than 1 dB coupling loss was achieved with an expanded beam size of 160 µm in diameter. Even with a relatively large lens offset of ∼35 µm, the detachable fiber array connectors showed good interchangeability. Such a coupling interface is expected to be solder-reflow compatible by replacing the plastic registration connectors with ceramic ones, making it a promising candidate for the solution to CPO fiber I/O.

Pass-block architecture for distributed-phase-reference quantum key distribution using silicon photonics.

Secure transmission of information is an indispensable part of the government and individual activities. Quantum key distribution (QKD), ascribed to its security based on the laws of quantum mechanics, has become an urgent research task to eliminate the rapidly growing threats of the ever-evolving large-scale quantum computing. In this Letter, we propose a silicon photonics transmitter using a pass-block architecture and experimentally demonstrated its performance with a demodulation chip for high-speed distributed-phase-reference QKD. We show estimated asymptotic secret key rates of 792 kbps for coherent-one-way protocol and 940 kbps for differential-phase-shift protocol over a 20 km emulated fiber link. This work provides new levels of flexibility, to the best of our knowledge, of using silicon photonics devices to incorporate QKD into future telecommunications networks.

Efficient, tunable flip-chip-integrated III-V/Si hybrid external-cavity laser array.

We demonstrate a surface-normal coupled tunable hybrid silicon laser array for the first time using passively-aligned, high-accuracy flip chip bonding. A 2x6 III-V reflective semiconductor optical amplifier (RSOA) array with integrated total internal reflection mirrors is bonded to a CMOS SOI chip with grating couplers and silicon ring reflectors to form a tunable hybrid external-cavity laser array. Waveguide-coupled wall plug efficiency (wcWPE) of 2% and output power of 3 mW has been achieved for all 12 lasers. We further improved the performance by reducing the thickness of metal/dielectric stacks and achieved 10mW output power and 5% wcWPE with the same integration techniques. This non-invasive, one-step back end of the line (BEOL) integration approach provides a promising solution to high density laser sources for future large-scale photonic integrated circuits.

Error-free operation of a polarization-insensitive 4λ x 25 Gbps silicon photonic WDM receiver with closed-loop thermal stabilization of Si microrings.

We report the first closed-loop operation of a 100 Gbps polarization-insensitive, 4-channel wavelength-tracking WDM receiver in silicon photonics platform. Error-free operation is achieved with input polarization scrambling over input wavelength change of 4.5 nm using efficient thermal tuning of Si microring demux, corresponding to greater than 60°C fluctuation in temperature.

An all-solid-state, WDM silicon photonic digital link for chip-to-chip communications.

We describe a multiwavelength hybrid-integrated solid-state link on a 3 µm silicon-on-insulator (SOI) nanophotonic platform. The link spans three chips and employs germanium-silicon electroabsorption waveguide modulators, silicon transport waveguides, echelle gratings for multiplexing and demultiplexing, and pure germanium waveguide photo-detectors. The 8λ WDM Tx and Rx components are interconnected via a routing "bridge" chip using edge-coupled optical proximity communication. The packaged, retimed digital WDM link is demonstrated at 10 Gb/s and 10(-12) BER, with three wavelength channels consuming an on-chip power below 1.5 pJ/bit, excluding the external laser power.

Microring-based multi-chip WDM photonic module.

We report on a packaged prototype of a WDM photonic transceiver. It is an all-solid state hybrid assembly based on 130nm SOI photonic circuitry integrated with a 40nm CMOS VLSI driver. Our prototype supports eight tunable WDM channels operating at 10Gb/s, each capable of both transmitting and receiving data on the same chip. We discuss two options to close the link using the optical fiber or a waveguide bridge chip. We provide integration details and supporting link measurement data to describe packaged photonic module and its power efficient functionality with its on-chip power per channel averaging 1.3pJ/bit, excluding off-chip laser electrical power.

Demonstration of 12.2% wall plug efficiency in uncooled single mode external-cavity tunable Si/III-V hybrid laser.

A Si/III-V hybrid laser has been a highly sought after device for energy-efficient and cost-effective high-speed silicon photonics communication. We present a high wall-plug efficiency external-cavity hybrid laser created by integrating an independently optimized SOI ring reflector and a III-V gain chip. In our demonstration, the uncooled integrated laser achieved a waveguide-coupled wall-plug efficiency of 12.2% at room temperature with an optical output power of ~10 mW. The laser operated single-mode near 1550 nm with a linewidth of 0.22 pm. This is a tunable light source with 8 nm wavelength tuning range. A proof-of-concept laser wavelength stabilization technique has also been demonstrated. Using a simple feedback loop, we achieved mode-hop-free operation in a packaged external-cavity hybrid laser as bias current was varied by 60mA.

A high-speed, tunable silicon photonic ring modulator integrated with ultra-efficient active wavelength control.

We report the first complete 10G silicon photonic ring modulator with integrated ultra-efficient CMOS driver and closed-loop wavelength control. A selective substrate removal technique was used to improve the ring tuning efficiency. Limited by the thermal tuner driver output power, a maximum open-loop tuning range of about 4.5nm was measured with about 14mW of total tuning power including the heater driver circuit power consumption. Stable wavelength locking was achieved with a low-power mixed-signal closed-loop wavelength controller. An active wavelength tracking range of > 500GHz was demonstrated with controller energy cost of only 20fJ/bit.

High power and widely tunable Si hybrid external-cavity laser for power efficient Si photonics WDM links.

A highly efficient silicon (Si) hybrid external cavity laser with a wavelength tunable ring reflector is fabricated on a complementary metal-oxide semiconductor (CMOS)-compatible Si-on-insulator (SOI) platform and experimental results with high output power are demonstrated. A III-V semiconductor gain chip is edge-coupled into a SOI cavity chip through a SiN(x) spot size converter and Si grating couplers are incorporated to enable wafer-scale characterization. The laser output power reaches 20 mW and the highest wall-plug efficiency of 7.8% is measured at 17.3 mW in un-cooled condition. The laser wavelength tuning ranges are 8 nm for the single ring reflector cavity and 35 nm for the vernier ring reflector cavity, respectively. The Si hybrid laser is a promising light source for energy-efficient Si CMOS photonic links.

Vertical-coupled high-efficiency tunable III-V- CMOS SOI hybrid external-cavity laser.

We demonstrate a hybrid III-V/SOI laser by vertically coupling a III-V RSOA chip with a SOI-CMOS chip containing a tunable wavelength selective reflector. We report a waveguide-coupled wall-plug-efficiency of 5.5% and output power of 10 mW. A silicon resistor-based microheater was integrated to thermally tune a ring resonator for precise lasing wavelength control. A high tuning efficiency of 2.2 nm/mW over a range of 18 nm was achieved by locally removing the SOI handler substrate. C-band single mode lasing was confirmed with a side mode suppression ratio of 35 dB. This grating coupler based vertical integration approach can be scaled up in two dimensions for efficient multi-wavelength sources in silicon photonics.

Improving CMOS-compatible Germanium photodetectors.

We report design improvements for evanescently coupled Germanium photodetectors grown at low temperature. The resulting photodetectors with 10 µm Ge length manufactured in a commercial CMOS process achieve >0.8 A/W responsivity over the entire C-band, with a device capacitance of <7 fF based on measured data.

Ultralow-loss, high-density SOI optical waveguide routing for macrochip interconnects.

We report optical waveguides up to one meter long with 0.026 dB/cm loss fabricated in a 300nm thick SOI CMOS process. Combined with tight bends and compact interlayer grating couplers, we demonstrate a complete toolbox for ultralow-loss, high-density waveguide routing for macrochip interconnects.

Enhanced optical bistability from self-heating due to free carrier absorption in substrate removed silicon ring modulators.

We show enhanced optical bistability induced by free carrier absorption from junction doping in substrate-removed silicon ring modulators. Such linear thermal effects dominate the loss in high-speed depletion silicon ring modulators. Optical bistability was observed with about 100 µW of input optical power. We further show that such thermal interactions causes data-dependent ring resonance shifts, and consequently severely degrade the data modulation quality at low speeds. The frequency response of this effect was measured to be about 100~200 kHz.

25Gb/s 1V-driving CMOS ring modulator with integrated thermal tuning.

We report a high-speed ring modulator that fits many of the ideal qualities for optical interconnect in future exascale supercomputers. The device was fabricated in a 130 nm SOI CMOS process, with 7.5 µm ring radius. Its high-speed section, employing PN junction that works at carrier-depletion mode, enables 25 Gb/s modulation and an extinction ratio >5 dB with only 1V peak-to-peak driving. Its thermal tuning section allows the device to work in broad wavelength range, with a tuning efficiency of 0.19 nm/mW. Based on microwave characterization and circuit modeling, the modulation energy is estimated ~7 fJ/bit. The whole device fits in a compact 400 µm2 footprint.

Ultra-efficient 10 Gb/s hybrid integrated silicon photonic transmitter and receiver.

Using low parasitic microsolder bumping, we hybrid integrated efficient photonic devices from different platforms with advanced 40 nm CMOS VLSI circuits to build ultra-low power silicon photonic transmitters and receivers for potential applications in high performance inter/intra-chip interconnects. We used a depletion racetrack ring modulator with improved electro-optic efficiency to allow stepper optical photo lithography for reduced fabrication complexity. Integrated with a low power cascode 2 V CMOS driver, the hybrid silicon photonic transmitter achieved better than 7 dB extinction ratio for 10 Gbps operation with a record low power consumption of 1.35 mW. A received power penalty of about 1 dB was measured for a BER of 10(-12) compared to an off-the-shelf lightwave LiNOb3 transmitter, which comes mostly from the non-perfect extinction ratio. Similarly, a Ge waveguide detector fabricated using 130 nm SOI CMOS process was integrated with low power VLSI circuits using hybrid bonding. The all CMOS hybrid silicon photonic receiver achieved sensitivity of -17 dBm for a BER of 10(-12) at 10 Gbps, consuming an ultra-low power of 3.95 mW (or 395 fJ/bit in energy efficiency). The scalable hybrid integration enables continued photonic device improvements by leveraging advanced CMOS technologies with maximum flexibility, which is critical for developing ultra-low power high performance photonic interconnects for future computing systems.

Submilliwatt, ultrafast and broadband electro-optic silicon switches.

We present a broadband 2x2 electro-optic silicon switch with an ultralow switching power and fast switching time based on a Mach-Zehnder interferometer (MZI). Forward-biased p-i-n junctions are employed to tune the phase of silicon waveguides in the MZI, to achieve a π-phase switching power of 0.6 mW with a drive voltage 0.83 V with a MZI arm length of 4 mm. The 10%-90% switching time is demonstrated to be 6 ns. Optical crosstalk levels lower than -17 dB are obtained for an optical bandwidth of 60 nm. The free carrier induced silicon refractive index change is extracted from the experimental results for the concentration range from 10(16) to 10(17) cm(-3). We find that at the concentration of 10(16) cm(-3), the index change is about twice that calculated by the commonly used index change equation.

Highly-efficient thermally-tuned resonant optical filters.

We demonstrate spectral tunability for microphotonic add-drop filters manufactured as ring resonators in a commercial 130 nm SOI CMOS technology. The filters are provisioned with integrated heaters built in CMOS for thermal tuning. Their thermal impedance has been dramatically increased by the selective removal of the SOI handler substrate under the device footprint using a bulk silicon micromachining process. An overall ~20x increase in the tuning efficiency has been demonstrated with a 100 µm radius ring as compared to a pre-micromachined device. A total of 3.9 mW of applied tuning power shifts the filter resonant peak across one free spectral node of the device. The Q-factor of the resonator remains unchanged after the co-integration process and hence this device geometry proves to be fully CMOS compatible. Additionally, after the cointegration process our result of 2π shift with 3.9 mW power is among the best tuning performances for this class of devices. Finally, we examine scaling the tuning efficiency versus device footprint to develop a different performance criterion for an easier comparison to evaluate thermal tuning. Our criterion is defined as the unit of power to shift the device resonance by a full 2π phase shift.

High-speed and compact silicon modulator based on a racetrack resonator with a 1 V drive voltage.

Fast, compact, and power-efficient silicon microcavity electro-optic modulators are expected to be critical components for chip-level optical interconnects. It is highly desirable that these modulators can be driven by voltage swings of 1 V or less to reduce power dissipation and make them compatible with voltage supply levels associated with current and future complementary metal-oxide-semiconductor technology nodes. Here, we present a silicon racetrack resonator modulator that achieves over 8 dB modulation depth at 12.5 Gbps with a 1 V swing. In addition, the use of a racetrack resonator geometry relaxes the tight lithography resolution requirements typically associated with microring resonators and enhances the ability to use common lithographic optical techniques for their fabrication.

Low power and compact reconfigurable multiplexing devices based on silicon microring resonators.

We present thermally reconfigurable multiplexing devices based on silicon microring resonators with low tuning power and low thermal crosstalk. Micro-heaters on top of the rings are employed to tune the resonant wavelengths through the thermo-optic effect of silicon. We achieve a low tuning power of 21 mW per free spectral range for a single ring by exploiting thermal isolation trenches close to the ring waveguides. Negligible thermal crosstalk is demonstrated for rings spaced by 15 microm, enabling compact multiplexing devices. The tuning time constant is demonstrated to be less than 10 micros.

Wavelength-tunable silicon microring modulator.

We present a wavelength-tunable, compact, high speed and low power silicon microring modulator. With a ring radius of 5 microm, we demonstrate a modulator with a high speed of 12.5 Gbps and a driving voltage of 3 V to achieve approximately 6 dB extinction ratio in high speed measurement. More importantly, tunability of the resonant wavelength is accomplished by means of a microheater on top of the ring, with an efficiency of 2.4 mW/nm (2.4 mW is needed to tune the resonant wavelength by 1 nm). This device aims to solve the narrow bandwidth problem of silicon microcavity modulators and increase the data bandwidth in optical interconnect systems.