RESUMO
We demonstrate an optical clock recovery circuit that extracts the line rate component on a per packet basis from short data packets at 40Gb/s. The circuit comprises a Fabry-Perot filter followed by a novel power limiting configuration, which in turn consists of a 5m highly nonlinear bismuth oxide fiber in cascade with an optical bandpass filter. Both experimental and simulation-based results are in close agreement and reveal that the proposed circuit acquires the timing information within only a small number of bits, yielding a packet clock for every respective data packet. Moreover, we investigate theoretically the scaling laws for the parameters of the circuit for operation beyond 40 Gb/s and present simulation results showing successful packet clock extraction for 160 Gb/s data packets. Finally, the circuit's potential for operation at 320 Gb/s is discussed, indicating that ultrafast packet clock recovery should be in principle feasible by exploiting the passive structure of the device and the fsec-scale nonlinear response of the optical fiber.
RESUMO
We demonstrate an all-optical, self-synchronization scheme for optical packet switched network nodes. It provides both the packet clock signal and the packet beginning, marker pulse. The circuit uses two hybridly integrated MZI switches and has been evaluated with synchronous, asynchronous and variable length, data packets at 10 Gb/s. It is compact and requires relatively low energies to operate.
RESUMO
We present and evaluate a compact, all-optical Clock and Data Recovery (CDR) circuit based on integrated Mach Zehnder interferometric switches. Successful operation for short packet-mode traffic of variable length and phase alignment is demonstrated. The acquired clock signal rises within 2 bits and decays within 15 bits, irrespective of packet length and phase. Error-free operation is demonstrated at 10 Gb/s.
