Practical hardware for evolvable robots.

The evolutionary robotics field offers the possibility of autonomously generating robots that are adapted to desired tasks by iteratively optimising across successive generations of robots with varying configurations until a high-performing candidate is found. The prohibitive time and cost of actually building this many robots means that most evolutionary robotics work is conducted in simulation, but to apply evolved robots to real-world problems, they must be implemented in hardware, which brings new challenges. This paper explores in detail the design of an example system for realising diverse evolved robot bodies, and specifically how this interacts with the evolutionary process. We discover that every aspect of the hardware implementation introduces constraints that change the evolutionary space, and exploring this interplay between hardware constraints and evolution is the key contribution of this paper. In simulation, any robot that can be defined by a suitable genetic representation can be implemented and evaluated, but in hardware, real-world limitations like manufacturing/assembly constraints and electrical power delivery mean that many of these robots cannot be built, or will malfunction in operation. This presents the novel challenge of how to constrain an evolutionary process within the space of evolvable phenotypes to only those regions that are practically feasible: the viable phenotype space. Methods of phenotype filtering and repair were introduced to address this, and found to degrade the diversity of the robot population and impede traversal of the exploration space. Furthermore, the degrees of freedom permitted by the hardware constraints were found to be poorly matched to the types of morphological variation that would be the most useful in the target environment. Consequently, the ability of the evolutionary process to generate robots with effective adaptations was greatly reduced. The conclusions from this are twofold. 1) Designing a hardware platform for evolving robots requires different thinking, in which all design decisions should be made with reference to their impact on the viable phenotype space. 2) It is insufficient to just evolve robots in simulation without detailed consideration of how they will be implemented in hardware, because the hardware constraints have a profound impact on the evolutionary space.

A Highly Pipelined and Highly Parallel VLSI Architecture of CABAC Encoder for UHDTV Applications.

Recently, specifically designed video codecs have been preferred due to the expansion of video data in Internet of Things (IoT) devices. Context Adaptive Binary Arithmetic Coding (CABAC) is the entropy coding module widely used in recent video coding standards such as HEVC/H.265 and VVC/H.266. CABAC is a well known throughput bottleneck due to its strong data dependencies. Because the required context model of the current bin often depends on the results of the previous bin, the context model cannot be prefetched early enough and then results in pipeline stalls. To solve this problem, we propose a prediction-based context model prefetching strategy, effectively eliminating the clock consumption of the contextual model for accessing data in memory. Moreover, we offer multi-result context model update (MCMU) to reduce the critical path delay of context model updates in multi-bin/clock architecture. Furthermore, we apply pre-range update and pre-renormalize techniques to reduce the multiplex BAE's route delay due to the incomplete reliance on the encoding process. Moreover, to further speed up the processing, we propose to process four regular and several bypass bins in parallel with a variable bypass bin incorporation (VBBI) technique. Finally, a quad-loop cache is developed to improve the compatibility of data interactions between the entropy encoder and other video encoder modules. As a result, the pipeline architecture based on the context model prefetching strategy can remove up to 45.66% of the coding time due to stalls of the regular bin, and the parallel architecture can also save 29.25% of the coding time due to model update on average under the condition that the Quantization Parameter (QP) is equal to 22. At the same time, the throughput of our proposed parallel architecture can reach 2191 Mbin/s, which is sufficient to meet the requirements of 8 K Ultra High Definition Television (UHDTV). Additionally, the hardware efficiency (Mbins/s per k gates) of the proposed architecture is higher than that of existing advanced pipeline and parallel architectures.

Robust electrical impedance tomography for biological application: A mini review.

Electrical impedance tomography (EIT) has been used by researchers across several areas because of its low-cost and no-radiation properties. Researchers use complex conductivity in bioimpedance experiments to evaluate changes in various indicators within the image target. The diverse volumes and edges of biological tissues and the large impedance range impose dedicated demands on hardware design. The EIT hardware with a high signal-to-noise ratio (SNR), fast scanning and suitable for the impedance range of the image target is a fundamental foundation that EIT research needs to be equipped with. Understanding the characteristics of this technique and state-of-the-art design will accelerate the development of the robust system and provide a guidance for the superior performance of next-generation EIT. This review explores the hardware strategies for EIT proposed in the literature.

Hardware-Based Architecture for DNN Wireless Communication Models.

Multiple Input Multiple Output Orthogonal Frequency Division Multiplexing (MIMO OFDM) is a key technology for wireless communication systems. However, because of the problem of a high peak-to-average power ratio (PAPR), OFDM symbols can be distorted at the MIMO OFDM transmitter. It degrades the signal detection and channel estimation performance at the MIMO OFDM receiver. In this paper, three deep neural network (DNN) models are proposed to solve the problem of non-linear distortions introduced by the power amplifier (PA) of the transmitters and replace the conventional digital signal processing (DSP) modules at the receivers in 2 × 2 MIMO OFDM and 4 × 4 MIMO OFDM systems. Proposed model type I uses the DNN model to de-map the signals at the receiver. Proposed model type II uses the DNN model to learn and filter out the channel noises at the receiver. Proposed model type III uses the DNN model to de-map and detect the signals at the receiver. All three model types attempt to solve the non-linear problem. The robust bit error rate (BER) performances of the proposed receivers are achieved through the software and hardware implementation results. In addition, we have also implemented appropriate hardware architectures for the proposed DNN models using special techniques, such as quantization and pipeline to check the feasibility in practice, which recent studies have not done. Our hardware architectures are successfully designed and implemented on the Virtex 7 vc709 FPGA board.

Improved Wearable Devices for Dietary Assessment Using a New Camera System.

An unhealthy diet is strongly linked to obesity and numerous chronic diseases. Currently, over two-thirds of American adults are overweight or obese. Although dietary assessment helps people improve nutrition and lifestyle, traditional methods for dietary assessment depend on self-report, which is inaccurate and often biased. In recent years, as electronics, information, and artificial intelligence (AI) technologies advanced rapidly, image-based objective dietary assessment using wearable electronic devices has become a powerful approach. However, research in this field has been focused on the developments of advanced algorithms to process image data. Few reports exist on the study of device hardware for the particular purpose of dietary assessment. In this work, we demonstrate that, with the current hardware design, there is a considerable risk of missing important dietary data owing to the common use of rectangular image screen and fixed camera orientation. We then present two designs of a new camera system to reduce data loss by generating circular images using rectangular image sensor chips. We also present a mechanical design that allows the camera orientation to be adjusted, adapting to differences among device wearers, such as gender, body height, and so on. Finally, we discuss the pros and cons of rectangular versus circular images with respect to information preservation and data processing using AI algorithms.

A Wearable, Multi-Frequency Device to Measure Muscle Activity Combining Simultaneous Electromyography and Electrical Impedance Myography.

The detection of muscle contraction and the estimation of muscle force are essential tasks in robot-assisted rehabilitation systems. The most commonly used method to investigate muscle contraction is surface electromyography (EMG), which, however, shows considerable disadvantages in predicting the muscle force, since unpredictable factors may influence the detected force but not necessarily the EMG data. Electrical impedance myography (EIM) investigates the change in electrical impedance during muscle activities and is another promising technique to investigate muscle functions. This paper introduces the design, development, and evaluation of a device that performs EMG and EIM simultaneously for more robust measurement of muscle conditions subject to artifacts. The device is light, wearable, and wireless and has a modular design, in which the EMG, EIM, micro-controller, and communication modules are stacked and interconnected through connectors. As a result, the EIM module measures the bioimpedance between 20 and 200 Ω with an error of less than 5% at 140 SPS. The settling time during the calibration phase of this module is less than 1000 ms. The EMG module captures the spectrum of the EMG signal between 20-150 Hz at 1 kSPS with an SNR of 67 dB. The micro-controller and communication module builds an ARM-Cortex M3 micro-controller which reads and transfers the captured data every 1 ms over RF (868 Mhz) with a baud rate of 500 kbps to a receptor connected to a PC. Preliminary measurements on a volunteer during leg extension, walking, and sit-to-stand showed the potential of the system to investigate muscle function by combining simultaneous EMG and EIM.

Real-time FPGA-based implementation of the AKAZE algorithm with nonlinear scale space generation using image partitioning.

The first step in a scale invariant image matching system is scale space generation. Nonlinear scale space generation algorithms such as AKAZE, reduce noise and distortion in different scales while retaining the borders and key-points of the image. An FPGA-based hardware architecture for AKAZE nonlinear scale space generation is proposed to speed up this algorithm for real-time applications. The three contributions of this work are (1) mapping the two passes of the AKAZE algorithm onto a hardware architecture that realizes parallel processing of multiple sections, (2) multi-scale line buffers which can be used for different scales, and (3) a time-sharing mechanism in the memory management unit to process multiple sections of the image in parallel. We propose a time-sharing mechanism for memory management to prevent artifacts as a result of separating the process of image partitioning. We also use approximations in the algorithm to make hardware implementation more efficient while maintaining the repeatability of the detection. A frame rate of 304 frames per second for a 1280 × 768 image resolution is achieved which is favorably faster in comparison with other work.

Highly parallelized memristive binary neural network.

At present, in the new hardware design work of deep learning, memristor as a non-volatile memory with computing power has become a research hotspot. The weights in the deep neural network are the floating-point number. Writing a floating-point value into a memristor will result in a loss of accuracy, and the writing process will take more time. The binarized neural network (BNN) binarizes the weights and activation values that were originally floating-point numbers to +1 and -1. This will greatly reduce the storage space consumption and time consumption of programming the resistance value of the memristor. Furthermore, this will help to simplify the programming of memristors in deep neural network circuits and speed up the inference process. This paper provides a complete solution for implementing memristive BNN. Furthermore, we improved the design of the memristor crossbar by converting the input feature map and kernel before performing the convolution operation that can ensure the sign of the input voltage of each port constant. Therefore, we do not need to determine the sign of the input voltage required by the port in advance which simplifies the process of inputting the feature map elements to each port of the crossbar in the form of voltage. At the same time, in order to ensure that the output of the current convolution layer can be directly used as the input of the next layer, we have added a corresponding processing circuit, which integrates batch-normalization and binarization operations.

Hardware and coding efficiency assessment of 3D-HEVC DIS tool using alternative similarity criteria.

3D-HEVC is the state-of-the-art standard to compress three-dimensional videos. One of the 3D-HEVC novel tools is the DIS tool, which is used to efficiently compress smooth and homogeneous areas of depth maps by using four different prediction modes. The decision of which DIS mode will be used is done through the SVDC similarity criterion in the DIS original definition. This article proposes the substitution of the complex SVDC criterion for simpler and more hardware friendly criteria as SATD, SSE, and SAD. These alternative criteria were evaluated in terms of encoding efficiency and hardware impacts in comparison with the SVDC. Dedicated DIS hardware were designed using each one of each criterion and these designs were described in VHDL and synthesized for TSMC 40 nm. The best results were found with SAD criteria, with losses of only 0.2% in coding efficiency and with expressive gains of more than 50 times in power and more than 35 times in area, when compared with SVDC. The reached results showed that the use of a simpler similarity criterion is an important alternative to be used in DIS tool, mainly if an efficient hardware design is required.

Multi-Frequency Magnetic Induction Tomography System and Algorithm for Imaging Metallic Objects.

Magnetic induction tomography (MIT) is largely focused on applications in biomedical and industrial process engineering. MIT has a great potential for imaging metallic samples; however, there are fewer developments directed toward the testing and monitoring of metal components. Eddy-current non-destructive testing is well established, showing that corrosion, fatigue and mechanical loading are detectable in metals. Applying the same principles to MIT would provide a useful imaging tool for determining the condition of metal components. A compact MIT instrument is described, including the design aspects and system performance characterisation, assessing dynamic range and signal quality. The image rendering ability is assessed using both external and internal object inclusions. A multi-frequency MIT system has similar capabilities as transient based pulsed eddy current instruments. The forward model for frequency swap multi-frequency is solved, using a computationally efficient numerical modelling with the edge-based finite elements method. The image reconstruction for spectral imaging is done by adaptation of a spectrally correlative base algorithm, providing whole spectrum data for the conductivity or permeability.

Learning automata based energy-efficient AI hardware design for IoT applications.

Energy efficiency continues to be the core design challenge for artificial intelligence (AI) hardware designers. In this paper, we propose a new AI hardware architecture targeting Internet of Things applications. The architecture is founded on the principle of learning automata, defined using propositional logic. The logic-based underpinning enables low-energy footprints as well as high learning accuracy during training and inference, which are crucial requirements for efficient AI with long operating life. We present the first insights into this new architecture in the form of a custom-designed integrated circuit for pervasive applications. Fundamental to this circuit is systematic encoding of binarized input data fed into maximally parallel logic blocks. The allocation of these blocks is optimized through a design exploration and automation flow using field programmable gate array-based fast prototypes and software simulations. The design flow allows for an expedited hyperparameter search for meeting the conflicting requirements of energy frugality and high accuracy. Extensive validations on the hardware implementation of the new architecture using single- and multi-class machine learning datasets show potential for significantly lower energy than the existing AI hardware architectures. In addition, we demonstrate test accuracy and robustness matching the software implementation, outperforming other state-of-the-art machine learning algorithms. This article is part of the theme issue 'Advanced electromagnetic non-destructive evaluation and smart monitoring'.

Anomaly Detection Trusted Hardware Sensors for Critical Infrastructure Legacy Devices.

Critical infrastructures and associated real time Informational systems need some security protection mechanisms that will be able to detect and respond to possible attacks. For this reason, Anomaly Detection Systems (ADS), as part of a Security Information and Event Management (SIEM) system, are needed for constantly monitoring and identifying potential threats inside an Information Technology (IT) system. Typically, ADS collect information from various sources within a CI system using security sensors or agents and correlate that information so as to identify anomaly events. Such sensors though in a CI setting (factories, power plants, remote locations) may be placed in open areas and left unattended, thus becoming targets themselves of security attacks. They can be tampering and malicious manipulated so that they provide false data that may lead an ADS or SIEM system to falsely comprehend the CI current security status. In this paper, we describe existing approaches on security monitoring in critical infrastructures and focus on how to collect security sensor-agent information in a secure and trusted way. We then introduce the concept of hardware assisted security sensor information collection that improves the level of trust (by hardware means) and also increases the responsiveness of the sensor. Thus, we propose a Hardware Security Token (HST) that when connected to a CI host, it acts as a secure anchor for security agent information collection. We describe the HST functionality, its association with a host device, its expected role and its log monitoring mechanism. We also provide information on how security can be established between the host device and the HST. Then, we introduce and describe the necessary host components that need to be established in order to guarantee a high security level and correct HST functionality. We also provide a realization-implementation of the HST overall concept in a FPGA SoC evaluation board and describe how the HST implementation can be controlled. In addition, in the paper, two case studies where the HST has been used in practice and its functionality have been validated (one case study on a real critical infrastructure test site and another where a critical industrial infrastructure was emulated in our lab) are described. Finally, results taken from these two case studies are presented, showing actual measurements for the in-field HST usage.

Crowbar hardware design enhancement for fault ride through capability in doubly fed induction generator-based wind turbines.

A crowbar circuit used in doubly fed induction generator (DFIG)-based wind turbines protects the system during transient stability. However, in a large power system, crowbar protection may be insufficient due to over-voltage and inrush currents occurring during balanced and unbalanced faults. Hence, in this study, a crowbar circuit was enhanced for fault ride through capability against balanced and unbalanced faults in a DFIG. The stator and rotor dynamic modeling used a crowbar hardware circuit design with rotor active impedance. Electromotive force voltages were used for the stator-rotor dynamics in the DFIG. Furthermore, crowbar resistance units were designed to meet the fault ride through DFIG requirement. The DFIG behaviors with and without the crowbar hardware circuit design were compared. The balanced and unbalanced faults were also compared in terms of behavior. Results showed that the circuit design of the crowbar hardware enabled the system to promptly become stable and eliminated the oscillations.

Two-Electrode ECG for Ambulatory Monitoring with Minimal Hardware Complexity.

This article introduces a two-electrode ground-free electrocardiogram (ECG) with minimal hardware complexity, which is ideal for wearable battery-powered devices. The main issue of ground-free measurements is the presence of noise. Therefore, noise suppression methods that can be employed for a two-electrode ECG acquisition system are discussed in detail. Experimental measurements of a living subject and patient simulator are used to investigate and compare the performance of the three proposed methods utilizing the ADS1191 analogue front-end for biopotential measurements. The resulting signals recorded for the simulator indicate that all three methods should be suitable for suppressing power-line noise. The Power Spectral Density (PSD) of the signals measured for a subject exhibits differences across methods; the signal power at 50 Hz is -28, -24.8, and -26 dB for the first, second, and third method, respectively. The digital postprocessing of measured signals acquired a high-quality ECG signal comparable to that of three-electrode sensing. The current consumption measurements demonstrate that all proposed two-electrode ECG solutions are appropriate as a battery-powered device (current consumption < 1.5 mA; sampling rate of 500 SPS). The first method, according to the results, is considered the most effective method in the suppression of power-line noise, current consumption, and hardware complexity.

Neural network design for energy-autonomous artificial intelligence applications using temporal encoding.

Neural networks (NNs) are steering a new generation of artificial intelligence (AI) applications at the micro-edge. Examples include wireless sensors, wearables and cybernetic systems that collect data and process them to support real-world decisions and controls. For energy autonomy, these applications are typically powered by energy harvesters. As harvesters and other power sources which provide energy autonomy inevitably have power variations, the circuits need to robustly operate over a dynamic power envelope. In other words, the NN hardware needs to be able to function correctly under unpredictable and variable supply voltages. In this paper, we propose a novel NN design approach using the principle of pulse width modulation (PWM). PWM signals represent information with their duty cycle values which may be made independent of the voltages and frequencies of the carrier signals. We design a PWM-based perceptron which can serve as the fundamental building block for NNs, by using an entirely new method of realizing arithmetic in the PWM domain. We analyse the proposed approach building from a 3 × 3 perceptron circuit to a complex multi-layer NN. Using handwritten character recognition as an exemplar of AI applications, we demonstrate the power elasticity, resilience and efficiency of the proposed NN design in the presence of functional and parametric variations including large voltage variations in the power supply. This article is part of the theme issue 'Harmonizing energy-autonomous computing and intelligence'.

The design and implementation of power control circuit of ultrasonic scalpel based on DSP / 中国医学装备

Objective:To independently develop a power control system of ultrasonic scalpel so as to reduce the energy consumption and maintain the normal temperature of ultrasonic scalpel.Methods:In this paper, the model of equivalent circuit of ultrasonic transducer nearby syntony was built up, and the hardware control system of ultrasonic scalpel based on digital signal processing (DSP) was designed.Results:Through testing the circuit and work performance of power control system, the series of parameters such as effective value and so on which were produced by this system could adjust frequency of power source in time and attain anticipative functional indicator, and it took the ultrasonic scalpel to work in syntonic situation.Conclusion:The tested indicators of power control system of ultrasonic scalpel based on the kernel design of DSP can attain anticipative requirement, and can take this system to work in syntonic situation.

Development and implementation of an 84-channel matrix gradient coil.

PURPOSE: Design, implement, integrate, and characterize a customized coil system that allows for generating spatial encoding magnetic fields (SEMs) in a highly-flexible fashion. METHODS: A gradient coil with a high number of individual elements was designed. Dimensions of the coil were chosen to mimic a whole-body gradient system, scaled down to a head insert. Mechanical shape and wire layout of each element were optimized to increase the local gradient strength while minimizing eddy current effects and simultaneously considering manufacturing constraints. RESULTS: Resulting wire layout and mechanical design is presented. A prototype matrix gradient coil with 12 × 7 = 84 elements consisting of two element types was realized and characterized. Measured eddy currents are <1% of the original field. The coil is shown to be capable of creating nonlinear, and linear SEMs. In a DSV of 0.22 m gradient strengths between 24 mT∕m and 78 mT∕m could be realized locally with maximum currents of 150 A. Initial proof-of-concept imaging experiments using linear and nonlinear encoding fields are demonstrated. CONCLUSION: A shielded matrix gradient coil setup capable of generating encoding fields in a highly-flexible manner was designed and implemented. The presented setup is expected to serve as a basis for validating novel imaging techniques that rely on nonlinear spatial encoding fields. Magn Reson Med 79:1181-1191, 2018. © 2017 International Society for Magnetic Resonance in Medicine.

Thermal sensation, rate of temperature change, and the heat dissipation design for tablet computers.

Past research has shown that the rate of change of skin surface temperature can affect thermal sensation. This study investigated users' thermal responses to a tablet heating surface with different heat pads and different temperature change rates. The test conditions included: A. keeping the surface at a constant 42 °C, B. increasing the surface temperature from 38 °C to 42 °C at a rate of 0.02 °C/s in progressive intervals, C. increasing the temperature at 0.15 °C/s in progressive intervals, and D. Heating two left and right side pads alternately from 38 °C to 42 °C at 0.15 °C/s in progressive intervals. Overall results showed the lowest temperature change rate of 0.02 °C/s was most preferred in terms of thermal comfort. The findings suggest a potential to improve user thermal experience by dissipating tablet computer heat at a lower temperature change rate, or by alternating the dissipation areas.

Hardware design of the cortical-diencephalic centre of the lower urinary tract neuroregulator system.

The neuroregulator system in humans controls organ and system functioning. This system comprises a set of neural centres that are distributed along the spinal cord and act independently together with their nerve interconnections. The centres involved in this task were isolated in previous studies through investigations of the functioning and composition of the neuroregulator system of the lower urinary tract to elucidate their individual performances and enable the creation of a general neuroregulator system model capable of operating at the neuronal level. Although the long-term goal of our research is the development of a system on chip (SoC) capable of behaving as a fully programmable neuroregulator system, this work is another step in which we test the viability of the hardware design of one of these neuroregulator centres (specifically the cortical-diencephalic centre) to achieve a first prototype and architectural proposal. To this end, the behaviour of this centre has been isolated, a hardware design implemented on FPGA has been proposed to create a prototype, a simulation environment has been built for the evaluation, and finally, the results have been analysed. This system verified that the functional behaviour corresponded to the expected behaviour in humans and that the operational requirements for the implementation were technically and architecturally viable.

On the use of inexact, pruned hardware in atmospheric modelling.

Inexact hardware design, which advocates trading the accuracy of computations in exchange for significant savings in area, power and/or performance of computing hardware, has received increasing prominence in several error-tolerant application domains, particularly those involving perceptual or statistical end-users. In this paper, we evaluate inexact hardware for its applicability in weather and climate modelling. We expand previous studies on inexact techniques, in particular probabilistic pruning, to floating point arithmetic units and derive several simulated set-ups of pruned hardware with reasonable levels of error for applications in atmospheric modelling. The set-up is tested on the Lorenz '96 model, a toy model for atmospheric dynamics, using software emulation for the proposed hardware. The results show that large parts of the computation tolerate the use of pruned hardware blocks without major changes in the quality of short- and long-time diagnostics, such as forecast errors and probability density functions. This could open the door to significant savings in computational cost and to higher resolution simulations with weather and climate models.