Design of a reversible single precision floating point subtractor. | Springerplus;3: 11, 2014 Jan 04. | MEDLINE

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Design of a reversible single precision floating point subtractor.

Anantha Lakshmi, Av; Sudha, Gf.

Affiliation

Anantha Lakshmi A; Department of Electronics and Communication Engineering, Pondicherry Engineering College, Puducherry, India.
Sudha G; Department of Electronics and Communication Engineering, Pondicherry Engineering College, Puducherry, India.

Springerplus ; 3: 11, 2014 Jan 04.

Article in En | MEDLINE | ID: mdl-24455466

Key words

FPGA; Reversible comparator; Reversible floating point subtractor; Reversible leading zero detector; Reversible logic; Reversible shift register

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Full text: 1 Collection: 01-internacional Database: MEDLINE Language: En Journal: Springerplus Year: 2014 Document type: Article Affiliation country: India Country of publication: Switzerland

Search on Google

Full text: 1 Collection: 01-internacional Database: MEDLINE Language: En Journal: Springerplus Year: 2014 Document type: Article Affiliation country: India Country of publication: Switzerland